Freescale Semiconductor
Data Sheet
Document Number: MSC7116
Rev. 13, 4/2008
MSC7116
Low-Cost 16-bit DSP with
DDR Controller and 10/100
Mbps Ethernet MAC
• StarCore
®
SC1400 DSP extended core with one SC1400 DSP
core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 192 Kbyte M2 memory for critical data and temporary data
buffering.
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
• Internal PLL generates up to 266 MHz clock for the SC1400 core
and up to 133 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
MAP-BGA–400
17 mm
×
17 mm
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
• Ethernet controller with support for 10/100 Mbps MII/RMII
designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,
and 802.3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual local area network (VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbound packets; and address recognition including
promiscuous, broadcast, individual address. hash/exact match,
and multicast hash match.
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I
2
C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booting external host via 8-bit or 16-bit access through
the HDI16, I
2
C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41
3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .54
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . .
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . .
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . .
Asynchronous Input Signal Timing . . . . . . . . . . . . . . .
Serial Management Channel Timing . . . . . . . . . . . . .
Read Timing Diagram, Single Data Strobe . . . . . . . .
Read Timing Diagram, Double Data Strobe . . . . . . . .
Write Timing Diagram, Single Data Strobe. . . . . . . . .
Write Timing Diagram, Double Data Strobe . . . . . . . .
Host DMA Read Timing Diagram, HPCR[OAD] = 0 . .
Host DMA Write Timing Diagram, HPCR[OAD] = 0 . .
I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . .
EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Test Clock Input Timing Diagram . . . . . . . . . . . . . . . .
Boundary Scan (JTAG) Timing Diagram . . . . . . . . . .
Test Access Port Timing Diagram . . . . . . . . . . . . . . .
TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . .
PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . .
SSTL Termination Techniques . . . . . . . . . . . . . . . . . .
SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
29
30
30
31
33
33
34
34
35
35
36
37
37
37
38
38
39
40
40
40
43
44
45
46
47
48
54
55
3
4
5
6
7
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
MSC7116 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
MSC7116 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
MSC7116 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram for a Reset Configuration Write . . . . 25
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26
DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27
DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 28
MSC7116 Data Sheet, Rev. 13
2
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