ATMEGA8535-16JUR datasheet, PDF

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ATMEGA8535-16JUR: DescriptionIC MCU 8BIT 8KB FLASH 44PLCC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，321 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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ATMEGA8535-16JUR Overview

IC MCU 8BIT 8KB FLASH 44PLCC

ATMEGA8535-16JUR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	GREEN, PLASTIC, MS-018AC, LCC-44
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	AVR RISC
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.586 mm
Humidity sensitivity level	2
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	512
rom(word)	4096
ROM programmability	FLASH
Maximum seat height	4.572 mm
speed	16 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.586 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

User Manual

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Features

•

High-performance, Low-power AVR

8-bit Microcontroller

•

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

– 8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM

– Programming Lock for Software Security

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels for TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP

Package Only

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF

Operating Voltages

– 2.7 - 5.5V for ATmega8535L

– 4.5 - 5.5V for ATmega8535

Speed Grades

– 0 - 8 MHz for ATmega8535L

– 0 - 16 MHz for ATmega8535

•

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

ATmega8535

ATmega8535L

•

2502K–AVR–10/06

The AVR core combines a rich instruction set with 32 general purpose working registers.

All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega8535 provides the following features: 8K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32

general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with

optional differential input stage with programmable gain in TQFP package, a program-

mable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software

selectable power saving modes. The Idle mode stops the CPU while allowing the

SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all

other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the

asynchronous timer continues to run, allowing the user to maintain a timer base while

the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and

all I/O modules except asynchronous timer and ADC, to minimize switching noise during

ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption. In Extended Standby mode, both the main Oscillator and the asynchro-

nous timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional nonvolatile memory programmer, or

by an On-chip Boot program running on the AVR core. The boot program can use any

interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535

is a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega8535 AVR is supported with a full suite of program and system develop-

ment tools including: C compilers, macro assemblers, program debugger/simulators, In-

Circuit Emulators, and evaluation kits.

AT90S8535 Compatibility

The ATmega8535 provides all the features of the AT90S8535. In addition, several new

features are added. The ATmega8535 is backward compatible with AT90S8535 in most

cases. However, some incompatibilities between the two microcontrollers exist. To

solve this problem, an AT90S8535 compatibility mode can be selected by programming

the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the

AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the

electrical characteristics differs between the two devices.

AT90S8535 Compatibility

Mode

Programming the S8535C fuse will change the following functionality:

•

The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page

45 for details.

The double buffering of the USART Receive Register is disabled. See “AVR USART

vs. AVR UART – Compatibility” on page 146 for details.

•

ATmega8535(L)

2502K–AVR–10/06

ATmega8535(L)

Pin Descriptions

GND

Port A (PA7..PA0)

Digital supply voltage.

Ground.

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port A output

buffers have symmetrical drive characteristics with both high sink and source capability.

When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source

current if the internal pull-up resistors are activated. The Port A pins are tri-stated when

a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega8535 as listed

on page 60.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8535 as listed

on page 64.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

15 on page 37. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally

connected to V

, even if the ADC is not used. If the ADC is used, it should be con-

nected to V

through a low-pass filter.

AREF is the analog reference pin for the A/D Converter.

Port D (PD7..PD0)

XTAL1

XTAL2

AVCC

AREF

2502K–AVR–10/06

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