EEWORLDEEWORLDEEWORLD

Part Number

Search

MBA0204AC5609FC100

Description
MBA/SMA 0204-50 1% HF C1 56R
CategoryPassive components   
File Size96KB,7 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
Download Datasheet Parametric View All

MBA0204AC5609FC100 Online Shopping

Suppliers Part Number Price MOQ In stock  
MBA0204AC5609FC100 - - View Buy Now

MBA0204AC5609FC100 Overview

MBA/SMA 0204-50 1% HF C1 56R

MBA0204AC5609FC100 Parametric

Parameter NameAttribute value
resistance56 Ohms
Tolerance±1%
Power (W)0.4W
componentthin film
characteristicradio frequency, high frequency
Temperature Coefficient±50ppm/°C
Operating temperature-55°C ~ 155°C
Package/casingAxial
Supplier device packagingAxial
size/dimensions0.063" diameter x 0.142" length (1.60mm x 3.60mm)
Height - Installation (maximum)-
Number of terminals2
failure rate-
Packaging
www.vishay.com
Vishay
Linear Leaded Resistors
DIMENSIONS OF AMMOPACK
P
N
M
Bandolier in ammopack
0.8 max. displacement
between any two resistors
0 + 1.6
0
S ± 0.1
1 max.
Dimensions in millimeters
Maximum 1 mm per 10 spacings
Maximum 0.5 mm per 5 spacings
a
B
1
A
B
2
Axial style on tape
DIMENSIONS
in millimeters - Resistor type, quantities and packaging dimensions for axial taped in ammopack
PRODUCT
TYPE
AC01
AC03
AC04
(1)
AC05
AC07
AC10
CBB 0207
MBA/SMA 0204
MBB/SMA 0207
MBE/SMA 0414
MRS16
(1)
QUANTITY
1000
500
500
500
500
250
1000
5000
5000
1000
5000
1000
100
1000
5000
1000
a
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
6 ± 0.5
PACKAGING DIMENSIONS
AXIAL TAPED ON BANDOLIER
S
A
|B
1
- B
2
|
63 ± 2.0
1.2
10
63 ± 2.0
1.2
10
63 ± 2.0
63 ± 2.0
74 ± 2.0
89 ± 4.0
52 +2 / -1
52 +2 / -1
52 +2 / -1
52 +2 / -1
52 +2 / -1
63 ± 2.0
52 +2 / -1
52 +2 / -1
52 +2 / -1
52 +2 / -1
52 +2 / -1
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
10
10
10
10
5
5
5
5
5
5
5
5
5
5
5
MRS25
(1)
5000
(1)
M
85
85
85
85
86
90
105
74
77
75
74
78
75
77
47
74
74
75
74
78
75
77
AMMOPACK
N
70
58
70
58
118
118
105
42
82
55
42
31
114
82
84
42
42
55
42
31
114
82
P
260
260
260
260
270
265
265
182
324
330
184
260
260
324
374
184
184
330
184
260
260
324
Notes
Manufacturing at different production locations may involve use of differently sized box. Please contact at below email for details
Document Number: 28721
1
For technical questions, contact:
filmresistorsleaded@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Revision: 15-May-2018
What does this error mean? How do I solve it? I'm a newbie!
Error: Can't name logic function sin_rom of instance "inst" -- function has same name as current design file Error: Can't elaborate user hierarchy "sin_rom:rom" What does this error mean and how do I ...
yangyi1818 FPGA/CPLD
Questions and Answers about RS-232 and RS-485 Interfaces
Data transmission between computers or between computers and terminals can be done by serial communication and parallel communication. Serial communication is widely used because it uses fewer lines a...
aone2008 Industrial Control Electronics
Opto promotes remote monitoring technology in mining industry
[Abstract] Opto is a remote monitoring solution provider, and is currently preparing to promote its technology in the mining industry. The mining industry, like other industrial enterprises, needs wei...
JasonYoo RF/Wirelessly
How to run tcl scripts in Synplify Pro?
Windows system. The version of Synplify Pro is 2013.3, and the license is node locked. I can run individual tcl commands one by one in the command line, but I cannot run the script file containing the...
azzzztec FPGA/CPLD
Convert a circuit block diagram into a circuit schematic in just a few steps
[color=#000][font=sans-serif]Step 1: Draw a circuit diagram based on the working principle of the circuit. This is relatively easy and easier to get online than a circuit diagram. The more specific th...
莫妮卡 Analogue and Mixed Signal
Ask for advice on FPGA download method
I'd like to ask you guys, will there be any problems if I remove the AS interface when using the FPGA board and download the JIC file to EPCS indirectly via JTAG?I saw that many people use it this way...
open82977352 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1895  2739  576  2344  1767  39  56  12  48  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号