XC2C256-6PQ208C datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> XC2C256-6PQ208C

XC2C256-6PQ208C: DescriptionFLASH PLD, 6 ns, PQFP100; CategoryProgrammable logic devices Programmable logic; File Size190KB，16 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC2C256-6PQ208C Overview

FLASH PLD, 6 ns, PQFP100

XC2C256-6PQ208C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	QFP
package instruction	28 X 28 MM, 0.50 MM PITCH, PLASTIC, QFP-208
Contacts	208
Reach Compliance Code	unknown
ECCN code	EAR99
Factory Lead Time	12 weeks
Other features	REAL DIGITAL DESIGN TECHNOLOGY
In-system programmable	YES
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
JTAG BST	YES
length	28 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	173
Number of macro cells	256
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 173 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	225
power supply	1.5/3.3,1.8 V
Programmable logic type	FLASH PLD
propagation delay	6 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	1.9 V
Minimum supply voltage	1.7 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm
Base Number Matches	1

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CoolRunner-II CPLD Family

DS090 (v3.1) September 11, 2008

Product Specification

SSTL2_1,SSTL3_1, and HSTL_1 on 128

macrocell and denser devices

- Hot pluggable

PLA architecture

- Superior pinout retention

- 100% product term routability across function block

Wide package availability including fine pitch:

- Chip Scale Package (CSP) BGA, Fine Line BGA,

TQFP, PQFP, VQFP, and QFN packages

- Pb-free available for all packages

Design entry/verification using Xilinx and industry

standard CAE tools

Free software support for all densities using Xilinx®

WebPACK™ tool

Industry leading nonvolatile 0.18 micron CMOS

process

- Guaranteed 1,000 program/erase cycles

- Guaranteed 20 year data retention

Features

•

Optimized for 1.8V systems

- Industry’s fastest low power CPLD

- Densities from 32 to 512 macrocells

Industry’s best 0.18 micron CMOS CPLD

- Optimized architecture for effective logic synthesis

- Multi-voltage I/O operation — 1.5V to 3.3V

Advanced system features

- Fastest in system programming

1.8V ISP using IEEE 1532 (JTAG) interface

- On-The-Fly Reconfiguration (OTF)

- IEEE1149.1 JTAG Boundary Scan Test

- Optional Schmitt trigger input (per pin)

- Multiple I/O banks on all devices

- Unsurpassed low power management

DataGATE external signal control

- Flexible clocking modes

Optional DualEDGE triggered registers

Clock divider (÷ 2,4,6,8,10,12,14,16)

CoolCLOCK

- Global signal options with macrocell control

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

- Abundant product term clocks, output enables and

set/resets

- Efficient control term clocks, output enables and

set/resets for each macrocell and shared across

function blocks

- Advanced design security

- Open-drain output option for Wired-OR and LED

drive

- Optional bus-hold, 3-state or weak pullup on select

I/O pins

- Optional configurable grounds on unused I/Os

- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels on all parts

XC2C32A

Macrocells

Max I/O

(ns)

SYSTEM1

(MHz)

3.8

1.9

3.7

323

XC2C64A

4.6

2.0

3.9

263

•

Family Overview

Xilinx CoolRunner™-II CPLDs deliver the high speed and

ease of use associated with the XC9500/XL/XV CPLD fam-

ily with the extremely low power versatility of the XPLA3

family in a single CPLD. This means that the exact same

parts can be used for high-speed data communications/

computing systems and leading edge portable products,

with the added benefit of In System Programming. Low

power consumption and high-speed operation are com-

bined into a single family that is easy to use and cost effec-

tive. Clocking techniques and other power saving features

extend the users’ power budget. The design features are

supported starting with Xilinx ISE® 4.1i WebPACK tool.

Additional details can be found in

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