DATASHEET
X9241A
Quad Digital Controlled Potentionmeters (XDCP™) Non-Volatile/Low
Power/2-Wire/64 Taps
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8164
Rev 7.00
August 17, 2015
Features
• Four potentiometers in one package
• 2-wire serial interface
• Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
• High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values
- 2k10k50kor combination
- Cascadable for values of 4kto 200k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
• Pb-free available (RoHS compliant)
Block Diagram
V
CC
V
SS
R0 R1
WIPER
COUNTER
REGISTER
(WCR)
V
H0
/R
H0
R0 R1
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 2
V
H2
/
R
H2
R2 R3
SCL
SDA
A0
A1
A2
A3
DATA
R0 R1
INTERFACE
AND
CONTROL
CIRCUITRY
V
L0
/R
L0
V
W0
/R
W0
R2 R3
V
L2
/R
L2
V
W2
/R
W2
8
V
H1
/R
H1
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 1
R0 R1
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 3
V
H3
/R
H3
R2 R3
V
L1
/R
L1
V
W1
/R
W1
R2 R3
V
L3
/R
L3
V
W3
/R
W3
FN8164 Rev 7.00
August 17, 2015
Page 1 of 17
X9241A
Ordering Information
PART NUMBER
X9241AMPZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMPIZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMSZ* (Note)
X9241AMSIZ* (Note)
X9241AMVZ (Note)
X9241AMVIZ* (Note)
X9241AWPIZ (Note)
X9241AWSZ* (Note)
X9241AWSIZ* (Note)
X9241AWVZ* (Note)
X9241AWVIZ* (Note)
X9241AYPZ (Note)
(No longer available,
recommended
replacement: X9241AYSIZ)
X9241AYSZ* (Note)
X9241AYSIZ* (Note)
X9241AYVZ (Note)
(No longer available,
recommended
replacement: X9241AYVIZ)
X9241AYVIZ* (Note)
X9241AUPZ (Note)
X9241AUPIZ (Note)
X9241AUSZ* (Note)
X9241AUSIZ* (Note)
X9241AUVZ* (Note)
(No longer available,
recommended
replacement:
X9241AUSZT1)
X9241AUVIZ* (Note)
PART MARKING
X9241AMPZ
V
CC
LIMITS
(V)
5 ±10%
Pot 0 = 2k
Pot 1 = 10k
X9241AMPIZ
Pot 2 = 10k
Pot 3 = 50k
-40 to +85
20 Ld PDIP***
POTENTIOMETER
ORGANIZATION
(k)
2/10/50
TEMP RANGE
(°C)
0 to +70
PACKAGE
(RoHS Compliant)
20 Ld PDIP***
X9241AMS Z
X9241AMSI Z
X9241AM VZ
X9241AM VIZ
X9241AWPIZ
X9241AWS Z
X9241AWSI Z
X9241AW VZ
X9241AW VIZ
X9241AYPZ
Pot 0 = 2k
Pot 1 = 2k
X9241AYS Z
X9241AYSI Z
X9241AY VZ
Pot 2 = 2k
Pot 3 = 2k
Pot 0 = 10k
Pot 1 = 10k
Pot 2 = 10k
Pot 3 = 10k
2
10
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
20 Ld PDIP***
0 to +70
-40 to +85
0 to +70
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
X9241AY VIZ
X9241AUPZ
X9241AUPIZ
X9241AUS Z
X9241AUSI Z
X9241AU VZ
5 ±10%
50
Pot 0 = 50k
Pot 1 = 50k
Pot 2 = 50k
Pot 3 = 50k
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
20 Ld TSSOP
20 Ld PDIP***
20 Ld PDIP***
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
X9241AU VIZ
-40 to +85
20 Ld TSSOP
*Add "T1" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8164 Rev 7.00
August 17, 2015
Page 2 of 17
X9241A
Pin Descriptions
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9241A.
Pin Names
SYMBOL
V
H0
/R
H0
to V
H3
/R
H3
,
V
L0
/R
L0
to V
L3
/R
L3
DESCRIPTION
Potentiometer Pins (terminal equivalent)
V
W0
/R
W0
to V
W3
/R
W3
Potentiometer Pins (wiper equivalent)
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
Principles of Operation
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9241A will be considered a slave
device in all applications.
Address
The Address inputs are used to set the least significant
4-bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9241A.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
TO V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
TO V
L3
/R
L3
)
The R
H
and R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
TO V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (t
LOW
). SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH (t
HIGH
). The X9241A continuously monitors the SDA
and SCL lines for the start condition and will not respond to any
command until this condition is met.
Pinout
X9241A
(20 LD DIP, SOIC, TSSOP)
TOP VIEW
V
W0
/R
W0
V
L0
/R
L0
V
H0
/R
H0
A0
A2
V
W1
/R
W1
V
L1
/R
L1
V
H1
/R
H1
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
X9241A
20
19
18
17
16
15
14
13
12
11
V
CC
V
W3
/R
W3
V
L3
/R
L3
V
H3
/R
H3
A1
A3
SCL
V
W2
/R
W2
V
L2
/R
L2
V
H2
/R
H2
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting 8-bits. The master generates a
ninth clock cycle and during this period the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
8-bits of data. See Figure 7.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and once
again after successful receipt of the command byte. If the
command is followed by a data byte the X9241A will respond
with a final acknowledge.
Pin Names
SYMBOL
SCL
SDA
A0 to A3
Serial Clock
Serial Data
Address
DESCRIPTION
Array Description
The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
FN8164 Rev 7.00
August 17, 2015
Page 3 of 17
X9241A
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (V
H
/R
H
and
V
L
/R
L
inputs).
At both ends of each array and between each resistor segment
is a FET switch connected to the wiper (V
W
/R
W
) output. Within
each individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper Counter
Register (WCR). The 6 least significant bits of the WCR are
decoded to select, and enable, 1 of 64 switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Flow 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
Device Addressing
Following a start condition the master must output the address
of the slave it is accessing. The most significant
4-bits of the slave address are the device type identifier (refer
to Figure 1). For the X9241A, this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
ACK
RETURNED?
YES
NO
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
PROCEED
PROCEED
The next 4-bits of the slave address are the device address.
The physical device address is defined by the state of the A0 to
A3 inputs. The X9241A compares the serial data stream with
the address input state; a successful compare of all 4 address
bits is required for the X9241A to respond with an
acknowledge.
Instruction Structure
The next byte sent to the X9241A contains the instruction and
register pointer information. The 4 most significant bits are the
instruction. The next 4-bits point to one of four pots and when
applicable they point to one of four associated registers. The
format is in Figure 2.
POTENTIOMETER
SELECT
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command, the X9241A
initiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition followed
by the device slave address. If the X9241A is still busy with the
write operation, no ACK will be returned. If the X9241A has
completed the write operation, an ACK will be returned and the
master can then proceed with the next operation.
I3
I2
I1
I0
P1
P0
R1
R0
INSTRUCTIONS
REGISTER
SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
The 4 high order bits define the instruction. The next 2-bits (P1
and P0) select which one of the four potentiometers is to be
affected by the instruction. The last 2-bits (R1 and R0) select
one of the four registers that are to be acted upon when a
register oriented instruction is issued.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 3.
These two-byte instructions exchange data between the WCR
and one of the data registers. A transfer from a Data Register to
a WCR is essentially a write to a static RAM. The response of
FN8164 Rev 7.00
August 17, 2015
Page 4 of 17
X9241A
the wiper to this action will be delayed t
STPWV
. A transfer from
WCR current wiper position to a Data Register is a write to
nonvolatile memory and takes a minimum of t
WR
to complete.
The transfer can occur between one of the four potentiometers
and one of its associated registers; or it may occur globally,
wherein the transfer occurs between all four of the
potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position of
the selected pot; Write WCR, change current wiper position of
the selected pot; Read Data Register, read the contents of the
selected nonvolatile register; Write Data Register, write a new
SCL
value to the selected Data Register. The sequence of
operations is shown in Figure 4.
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9241A has
responded with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL
clock pulse (t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
/R
H
terminal.
Similarly, for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards the
V
L
/R
L
terminal. A detailed illustration of the sequence and
timing for this operation is shown in Figures 5 and 6
respectively.
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1
P0
R1
R0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1 P0
R1 R0
A
C
K
CM DW D5 D4
D3
D2
D1 D0
A
C
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1
P0
X
R1
X
R0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
FN8164 Rev 7.00
August 17, 2015
Page 5 of 17
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