S25FL116K/S25FL132K/S25FL164K
16-Mbit (2 Mbyte)/32-Mbit (4 Mbyte)/
64-Mbit (8 Mbyte), 3.0 V, SPI Flash Memory
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede the
S25FL1-K family. These are the factory-recommended migration paths. Please refer to the S25FL-L Family datasheets for
specifications and ordering information.
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Command subset and footprint compatible with S25FL-K
Read
– Normal Read (Serial):
– 50 MHz clock rate (40 °C to +85 °C/105 °C)
– Fast Read (Serial):
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– Dual Read:
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– Quad Read:
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– 54 MB/s maximum continuous data transfer rate
(40 °C to +85 °C/105 °C)
– Efficient Execute-In-Place (XIP)
– Continuous and wrapped read modes
– Serial Flash Discoverable Parameters (SFDP)
Program
– Serial-input Page Program (up to 256 bytes)
– Program Suspend and Resume
Erase
– Uniform sector erase (4 kB)
– Uniform block erase (64 kB)
– Chip erase
– Erase Suspend and Resume
Cycling Endurance
– 100K Program-Erase cycles, minimum
Data Retention
– 20-year data retention, minimum
Security
– Three 256-byte Security Registers with OTP protection
– Low supply voltage protection of the entire memory
– Pointer-based security protection feature (S25FL132K
and
S25FL164K)
– Top / Bottom relative Block Protection Range, 4 kB to all of
memory
– 8-Byte Unique ID for each device
– Non-volatile Status Register bits control protection modes
– Software command protection
– Hardware input signal protection
– Lock-Down until power cycle protection
– OTP protection of security registers
90 nm Floating Gate Technology
Single Supply Voltage
– 2.7 V to 3.6 V (Industrial, Industrial Plus, and Extended
temperature range)
– 2.6 V to 3.6 V (Extended temperature range)
Temperature Ranges
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C))
Package Options
– S25FL116K
– 8-lead SOIC (150 mil) – SOA008
– 8-lead SOIC (208 mil) – SOC008
– 8-contact WSON 5 mm x 6 mm – WND008
– 24-ball BGA 6 mm
8 mm – FAB024 and FAC024
– KGD / KGW
– S25FL132K
– 8-lead SOIC (150 mil) – SOA008
– 8-lead SOIC (208 mil) – SOC008
– 8-contact USON 4 mm
4 mm – UNF008
– 8-contact WSON 5 mm
6 mm – WND008
– 24-ball BGA 6 mm
8 mm – FAB024 and FAC024
– KGD / KGW
– S25FL164K
– 8-lead SOIC (208 mil) – SOC008
– 16-lead SOIC (300 mil) – SO3016
– 8-contact WSON 5 mm
6 mm – WND008
–
24-ball BGA 6 mm
8 mm – FAB024 and FAC024
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Cypress Semiconductor Corporation
Document Number: 002-00497 Rev. *H
•
198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised May 19, 2017
S25FL116K/S25FL132K/S25FL164K
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
I/O
WP#/IO2
HOLD#/IO3
Control
Logic
X Decoders
Memory
Y Decoders
Data Latch
Performance Summary
Maximum Read Rates (V
CC
= 2.7 V to 3.6 V, 85 °C/105 °C)
Command
Read
Fast Read
Dual Read
Quad Read
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Clock Rate (MHz)
50
108
108
108
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Data Path
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Mbytes/s
6.25
13.5
27
54
Typical Program and Erase Rates (V
CC
= 2.7 V to 3.6 V, 85 °C/105 °C)
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kbytes/s
365
81
131
Page Programming (256-byte page buffer)
64-kbyte Sector Erase
Typical Current Consumption (V
CC
= 2.7 V to 3.6 V, 85 °C/105 °C)
Operation
Serial Read 50 MHz
Serial Read 108 MHz
Dual Read 108 MHz
Quad Read 108 MHz
Program
Erase
Standby
Deep-Power Down
Current (mA)
7
12
14
16
20
20
0.015
0.002
Document Number: 002-00497 Rev. *H
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4-kbyte Sector Erase
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S25FL116K/S25FL132K/S25FL164K
Contents
1.
1.1
1.2
1.3
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.
5.1
General Description.....................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
5
6
7
5.2
6.
6.1
6.2
6.3
6.4
Physical Diagrams ........................................................ 31
Address Space Maps..................................................
38
Overview....................................................................... 38
Flash Memory Array...................................................... 38
Security Registers......................................................... 39
Security Register 0 — Serial Flash
Discoverable Parameters
(SFDP — JEDEC JESD216B) ...................................... 39
Status Registers ........................................................... 49
Device Identification...................................................... 59
Functional Description
............................................... 60
SPI Operations ............................................................. 60
Write Protection ............................................................ 61
Status Registers ........................................................... 61
Commands
.................................................................. 62
Configuration and Status Commands ........................... 64
Program and Erase Commands ................................... 67
Read Commands .......................................................... 70
Reset Commands ......................................................... 75
ID and Security Commands .......................................... 77
Set Block / Pointer Protection (39h)
— S25FL132K and S25FL164K ................................... 81
Data Integrity...............................................................
83
Erase Endurance .......................................................... 83
Data Retention .............................................................. 83
Initial Delivery State ...................................................... 83
Ordering Information
.................................................. 84
Physical Interface
...................................................... 29
Connection Diagrams .................................................. 29
Document Number: 002-00497 Rev. *H
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Electrical Characteristics
..........................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Operating Ranges........................................................
DC Electrical Characteristics .......................................
AC Measurement Conditions .......................................
Power-Up Timing .........................................................
Power-On (Cold) Reset................................................
AC Electrical Characteristics........................................
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Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Status Register Effects on the Interface ......................
Data Protection ............................................................
12
12
12
16
19
19
20
20
21
21
22
23
24
25
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9.
9.1
9.2
9.3
10.
11. Revision History..........................................................
87
Document History Page 87
Sales, Solutions, and Legal Information .......................... 90
Worldwide Sales and Design Support ........................... 90
Products ........................................................................ 90
PSoC® Solutions .......................................................... 90
Cypress Developer Community ..................................... 90
Technical Support ......................................................... 90
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Signal Descriptions
..................................................... 8
Input / Output Summary................................................. 8
Address and Data Configuration.................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1................................................. 9
Write Protect (WP#) / IO2 .............................................. 9
HOLD# / IO3 ................................................................ 10
Core and I/O Signal Voltage Supply (V
CC
) .................. 10
Supply and Signal Ground (V
SS
) ................................. 10
Not Connected (NC) .................................................... 10
Reserved for Future Use (RFU)................................... 10
Do Not Use (DNU) ....................................................... 11
Block Diagrams............................................................ 11
6.5
6.6
7.
7.1
7.2
7.3
8.
8.1
8.2
8.3
8.4
8.5
8.6
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S25FL116K/S25FL132K/S25FL164K
1.
General Description
The S25FL1-K of non-volatile flash memory devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI
single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O
or QIO) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO.
The SPI-MIO protocols use only 4 to 6 signals:
Chip Select (CS#)
Serial Clock (SCK)
– IO0 (SI)
– IO1 (SO)
– IO2 (WP#)
– IO3 (HOLD#)
The SIO protocol uses Serial Input (SI) and Serial Output (SO) for data transfer. The DIO protocols use IO0 and IO1 to input or
output two bits of data in each clock cycle.
Serial Data
The HOLD# input signal option allows commands to be suspended and resumed on any clock cycle.
The QIO protocols use all of the data signals (IO0 to IO3) to transfer 4 bits in each clock cycle. When the QIO protocols are enabled
the WP# and HOLD# inputs and features are disabled.
Single bit data path = 13.5 Mbytes/s
Dual bit data path = 27 Mbytes/s
Quad bit data path = 54 Mbytes/s
Support JEDEC standard manufacturer and device type identification.
Program pages of 256 bytes each. One to 256 bytes can be programmed in each Page Program operation. Pages can be
erased in groups of 16 (4-kB aligned sector erase), groups of 256 (64-kB aligned block erase), or the entire chip (chip erase).
The S25FL1-K devices operate on a single 2.6V/2.7V to 3.6V power supply and all devices are offered in space-saving
packages.
Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer
flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing
code directly (XIP), and storing reprogrammable data.
Document Number: 002-00497 Rev. *H
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The S25FL1-K:
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Executing code directly from flash memory is often called execute-In-Place or XIP. By using S25FL1-K devices at the higher clock
rates supported, with QIO commands, the command read transfer rate can match or exceed traditional x8 or x16 parallel interface,
asynchronous, NOR flash memories, while reducing signal count dramatically. The Continuous Read Mode allows for random
memory access with as few as 8-clocks of overhead for each access, providing efficient XIP operation. The Wrapped Read mode
provides efficient instruction or data cache refill via a fast read of the critical byte that causes a cache miss, followed by reading all
other bytes in the same cache line in a single read command.
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Clock frequency of up to 108 MHz is supported, allowing data transfer rates up to:
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The Write Protect (WP#) input signal option allows hardware control over data protection. Software controlled commands can also
manage data protection.
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S25FL116K/S25FL132K/S25FL164K
1.1
1.1.1
Migration Notes
Features Comparison
The S25FL1-K is command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1. FL Generations Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed
Fast Read Speed
Dual Read Speed
Quad Read Speed
Program Buffer Size
Page Programming Time
(typ.)
Program Suspend / Resume
Erase Sector Size
Parameter Sector Size
Sector Erase Time (typ.)
Erase Suspend / Resume
OTP Size
Operating Temperature
S25FL1-K
90 nm
Floating Gate
In Production
16 Mbit - 64 Mbit
x1, x2, x4
2.6V / 2.7V - 3.6V
6 MB/s (50 MHz)
13.5 MB/s (108 MHz)
27 MB/s (108 MHz)
54 MB/s (108 MHz at 85°C/105°C)
256B
700 µs (256B)
Yes
4 kB / 64 kB
N/A
Yes
S25FL-K
90 nm
Floating Gate
In Production
4 Mbit - 128 Mbit
2.7V - 3.6V
x1, x2, x4
S25FL-P
90 nm
MirrorBit
®
In Production
32 Mbit - 256 Mbit
x1, x2, x4
2.7V - 3.6V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
256B
1500 µs (256B)
No
64 kB / 256 kB
4 kB
500 ms (64 kB)
No
506B
-40°C to +85°C / +105°C
6 MB/s (50 MHz)
13 MB/s (104 MHz)
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52 MB/s (104 MHz)
256B
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4 kB / 32 kB / 64 kB
N/A
30 ms (4 kB), 150 ms (64 kB)
Yes
768B (3 x 256B)
-40°C to +85°C
50 ms (4 kB), 500 ms (64 kB)
768B (3 x 256B)
2. S25FL1-K family devices can erase 4-kB sectors in groups of 64 kB.
3. S25FL-P has either 64-kB or 256-kB uniform sectors depending on an ordering option.
4. Refer to individual data sheets for further details.
1.1.2
1.1.2.1
Known Feature Differences from Prior Generations
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is the same for the S25FL1-K and the S25FL-K but different for
the S25FL-P.
Document Number: 002-00497 Rev. *H
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Notes:
1. S25FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
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-40°C to +85°C / +105°C
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Yes
26 MB/s (104 MHz)
700 µs (256B)
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