®
X4043, X4045
4k, 512 x 8 Bit
Data Sheet
March 16, 2006
FN8118.2
CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lock
™
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
Status
Register
EEPROM Array
2Kbits 1Kb 1Kb
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
falls below the minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Five industry stan-
dard V
TRIP
thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
RESET (X4043)
RESET (X4045)
Reset &
Watchdog
Timebase
SCL
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4043, X4045
Ordering Information
PART NUMBER RESET
(ACTIVE LOW)
X4043S8-4.5A
X4043S8Z-4.5A (Note)
X4043S8I-4.5A
PART
MARKING
X4043 AL
X4043 Z AL
X4043 AM
PART NUMBER
RESET (ACTIVE HIGH)
X4045S8-4.5A
PART
MARKING
X4045 AL
V
CC
V
TRIP
RANGE (V) RANGE (V)
4.5-5.5
4.5-4.75
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
4.5-5.5
4.25-4.5
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
2.7-5.5
2.85-3.0
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
X4045S8Z-4.5A (Note) X4045 Z AL
X4045S8I-4.5A
X4045 AM
X4043S8IZ-4.5A (Note) X4043 Z AM
X4043M8-4.5A
X4043M8Z-4.5A (Note)
X4043M8I-4.5A
ADA
DAZ
ADB
X4045S8IZ-4.5A (Note) X4045 Z AM
X4045M8-4.5A
ADJ
X4045M8Z-4.5A (Note) DBH
X4045M8I-4.5A
ADK
X4043M8IZ-4.5A (Note) DAU
X4043P-4.5A
X4043PZ-4.5A (Note)
X4043PI-4.5A
X4043PIZ-4.5A (Note)
X4043S8*
X4043S8Z* (Note)
X4043S8I*
X4043S8IZ* (Note)
X4043M8
X4043M8Z* (Note)
X4043M8I
X4043M8IZ (Note)
X4043P
X4043PZ (Note)
X4043PI
X4043PIZ (Note)
X4043S8-2.7A*
X4043P AL
X4045M8IZ-4.5A (Note) DBE
X4045P-4.5A
X4045P AL
X4045P Z AL
X4045P AM
X4045P Z AM
X4045
X4045 Z
X4045 I
X4045 Z I
ADL
DBD
ADM
DBA
X4045P
X4045P Z
X4045P I
X4045P Z I
X4045 AN
X4043P Z AL X4045PZ-4.5A (Note)
X4043P AM
X4045PI-4.5A
X4043P Z AM X4045PIZ-4.5A (Note)
X4043
X4043 Z
X4043 I
X4043 Z I
ADC
DAW
ADD
DAR
X4043P Z
X4043P
X4043P I
X4043P Z I
X4043 AN
X4045S8*
X4045S8Z* (Note)
X4045S8I
X4045S8IZ (Note)
X4045M8
X4045M8Z (Note)
X4045M8I
X4045M8IZ (Note)
X4045P
X4045PZ (Note)
X4045PI
X4045PIZ (Note)
X4045S8-2.7A
X4043S8Z-2.7A* (Note) X4043 Z AN
X4043S8I-2.7A*
X4043 AP
X4045S8Z-2.7A (Note) X4045 Z AN
X4045S8I-2.7A
X4045 AP
X4043S8IZ-2.7A* (Note) X4043 Z AP
X4043M8-2.7A
X4043M8Z-2.7A (Note)
X4043M8I-2.7A
ADE
DAY
ADF
X4045S8IZ-2.7A (Note) X4045 Z AP
X4045M8-2.7A
AND
X4045M8Z-2.7A (Note) DBG
X4045M8I-2.7A
ADO
X4043M8IZ-2.7A (Note) DAT
X4043P-2.7A
X4043PZ-2.7A (Note)
X4043PI-2.7A
X4043PIZ-2.7A (Note)
X4043P AN
X4045M8IZ-2.7A (Note) DBC
X4045P-2.7A
X4045P AN
X4045P Z AN
X4045P AP
X4045P Z AP
X4043P Z AN X4045PZ-2.7A (Note)
X4043P AP
X4045PI-2.7A
X4043P Z AP X4045PIZ-2.7A (Note)
2
FN8118.2
March 16, 2006
X4043, X4045
Ordering Information
PART NUMBER RESET
(ACTIVE LOW)
X4043S8-2.7*
X4043S8Z-2.7* (Note)
X4043S8I-2.7
X4043S8IZ-2.7 (Note)
X4043M8-2.7
X4043M8Z-2.7 (Note)
X4043M8I-2.7
X4043M8IZ-2.7(Note)
X4043P-2.7
X4043PZ-2.7 (Note)
X4043PI-2.7
X4043PIZ-2.7 (Note)
PART
MARKING
X4043 F
X4043 Z F
X4043 G
X4043 Z G
ADG
DAX
ADH
DAS
X4043P F
X4043P Z F
X4043P G
X4043P Z G
PART NUMBER
RESET (ACTIVE HIGH)
X4045S8-2.7*
X4045S8Z-2.7* (Note)
X4045S8I-2.7
X4045S8IZ-2.7 (Note)
X4045M8-2.7
X4045M8Z-2.7 (Note)
X4045M8I-2.7
X4045M8IZ-2.7 (Note)
X4045P-2.7
X4045PZ-2.7 (Note)
X4045PI-2.7
X4045PIZ-2.7 (Note)
PART
MARKING
X4045 F
X4045 Z F
X4045 G
X4045 Z G
ADP
DBF
ADQ
DBB
X4045P F
X4045P Z F
X4045P G
X4045P Z G
V
CC
V
TRIP
RANGE (V) RANGE (V)
2.7-5.5
2.55-2.7
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN8118.2
March 16, 2006
X4043, X4045
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on an I
2
C bus.
The device utilizes Intersil’s proprietary Direct
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
Write
™
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP, PDIP
NC
NC
RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Pin
(SOIC/MSOP/DIP)
1
2
3
Name
NC
NC
RESET/RESET
No internal connections
No internal connections
Function
Reset Output.
RESET is an active LOW, open drain output which goes active
whenever V
CC
falls below V
TRIP
. It will remain active until V
CC
rises above the
V
TRIP
for t
PURST
. RESET/RESET goes active if the Watchdog Timer is enabled
and SDA remains either HIGH or LOW longer than the selectable Watchdog time
out period. RESET/RESET goes active on power-uppower-up and remains
active for 250ms after the power supply stabilizes. RESET is an active high open
drain output. An external pull up resistor is required on the RESET/RESET pin.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Serial Clock.
The Serial Clock input controls the serial bus timing for data input and
output.
Write Protect.
WP HIGH prevents writes to any location in the device (including
the control register). Connect WP pin to V
SS
when it is not used.
Supply Voltage
4
5
V
SS
SDA
6
7
8
SCL
WP
V
CC
4
FN8118.2
March 16, 2006
X4043, X4045
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V
CC
exceeds the device V
TRIP
threshold value
for
200ms
(nominal)
the
circuit
releases
RESET/RESET allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
.6µs
SCL
1.3µs
SDA
Start
WDT Reset
Stop
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V
CC
< V
TRIP
), any in-progress com-
munications are terminated. While V
CC
< V
TRIP
, no new
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
TRIP
Programming
The X4043/45 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.
Figure 2. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
WP
V
P
= 15-18V
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
01h
00h
5
FN8118.2
March 16, 2006
Embedded System
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