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ATF1504AS-15JC68

Description
IC CPLD 64MC 15NS 68PLCC
Categorysemiconductor    Programmable logic devices   
File Size371KB,33 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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ATF1504AS-15JC68 Overview

IC CPLD 64MC 15NS 68PLCC

ATF1504AS-15JC68 Parametric

Parameter NameAttribute value
Programmable typeIn-system programmable (minimum 10,000 program/erase cycles)
Delay time tpd(1) maximum15ns
Supply voltage - internal4.75 V ~ 5.25 V
Number of macro cells64
Number of I/Os48
Operating temperature0°C ~ 70°C(TA)
Installation typesurface mount
Package/casing68-LCC (J lead)
Supplier device packaging68-PLCC(24.23x24.23)
Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3V or 5.0V I/O Pins
Security Fuse Feature
High-
performance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent – Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0950N–PLD–07/02
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