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DS026 (v4.1) December 15, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1
XC18V00 Series In-System Programmable Configuration PROMs
R
Pinout and Pin Description
Table 1
provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1:
Pin Names and Descriptions
Pin
Name
D0
Boundary
Scan
Order
4
3
D1
6
5
D2
2
1
D3
8
7
D4
24
23
D5
10
9
D6
17
16
D7
14
13
CLK
0
44-pin
VQFP
40
44-pin
PLCC
2
20-pin
SOIC &
PLCC
1
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Pin Description
D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
D0-D7 are the output pins to provide
parallel data for configuring a Xilinx
FPGA in Slave-Parallel/SelectMap mode.
D1-D7 remain in HIGHZ state when the
PROM operates in serial mode.
D1-D7 can be left unconnected when the
PROM is used in serial mode.
29
35
16
42
4
2
27
33
15
9
15
7
(1)
25
31
14
14
20
9
19
25
12
Each rising edge on the CLK input
increments the internal address counter if
both CE is Low and OE/RESET is High.
When Low, this input holds the address
counter reset and the DATA output is in a
high-impedance state. This is a
bidirectional open-drain pin that is held
Low while the PROM is reset. Polarity is
NOT programmable.
When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are
put in a high-impedance state.
43
5
3
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
2
www.xilinx.com
1-800-255-7778
DS026 (v4.1) December 15, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
44-pin
VQFP
10
44-pin
PLCC
16
20-pin
SOIC &
PLCC
7
(1)
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
Pin Description
Allows JTAG CONFIG instruction to
initiate FPGA configuration without
powering down FPGA. This is an
open-drain output that is pulsed Low by
the JTAG CONFIG command.
Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the
chain. This output is Low when CE is Low
and OE/RESET input is High, AND the
internal address counter has been
incremented beyond its Terminal Count
(TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
CEO
12
11
21
27
13
GND
TMS
MODE
SELECT
6, 18, 28 &
41
5
3, 12, 24
& 34
11
11
5
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic “1” to the
device if the pin is not driven.
This pin is the JTAG test clock. It
sequences the TAP controller and all the
JTAG test and programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin
is not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50K ohm resistive pull-up on it
to provide a logic “1” to the system if the
pin is not driven.
Positive 3.3V supply voltage for internal
logic.
Positive 3.3V or 2.5V supply voltage
connected to the input buffers
(2)
and
output voltage drivers.
No connects.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CCINT
V
CCO
17, 35 &
38
(3)
8, 16, 26 &
36
1, 2, 4,
11, 12, 20,
22, 23, 24,
30, 32, 33,
34, 37, 39,
44
23, 41 &
44
(3)
14, 22, 32
& 42
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
18 & 20
(3)
19
NC
Notes:
1.
2.
3.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES 0502x093h, the input buffers are supplied by V
CCINT
.
For devices with IDCODES, 0503x093h, these V
CCINT
pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package and pin 20 in 20-pin SOIC and20-pin PLCC packages.
DS026 (v4.1) December 15, 2003
Product Specification
www.xilinx.com
1-800-255-7778
3
XC18V00 Series In-System Programmable Configuration PROMs
R
Pinout Diagrams
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
OE/RESET
D6
CE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
V
CCO
VCCINT*
NC
18
19
20
21
22
23
24
25
26
27
28
3
2
1
20
19
CLK
D2
D0
VCCINT*
VCCO
18
PC20
17
Top View
16
15
14
NC
NC
TDI
NC
TMS
GND
TCK
V
CCO
D4
CF
NC
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
39
38
37
36
35
34
33
32
31
30
29
NC
NC
TDO
NC
D1
GND
D3
V
CCO
D5
NC
NC
SO20
Top
View
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
DS026_14_060403
6
5
4
3
2
1
44
43
42
41
40
*See pin descriptions.
*See pin descriptions.
DS026_12_060403
*See pin descriptions.
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
V
CCO
VCCINT*
NC
D6
CE
GND
D7
CEO
9
10
11
12
13
TDI
TMS
TCK
D4/CF*
OE/RESET
4
5
6
7
8
VCCINT*
TDO
D1
D3
D5
NC
OE/RESET
D6
CE
V
CCO
VCCINT*
GND
D7
NC
CEO
NC
DS026_15_060403
NC
NC
TDI
NC
TMS
GND
TCK
V
CCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
VQ44
Top View
33
32
31
30
29
28
27
26
25
24
23
NC
NC
TDO
NC
D1
GND
D3
V
CCO
D5
NC
NC
NC
OE/RESET
D6
CE
V
CCO
VCCINT*
GND
D7
NC
CEO
NC
4
12
13
14
15
16
17
18
19
20
21
22
*See pin descriptions.
DS026_13_060403
www.xilinx.com
1-800-255-7778
DS026 (v4.1) December 15, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
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