XC18V512SO20I datasheet, PDF - EEWORLD Datasheet

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XC18V512SO20I: DescriptionIC PROM SER I-TEMP 3.3V 20-SOIC; Categorystorage storage; File Size204KB，21 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC18V512SO20I Overview

IC PROM SER I-TEMP 3.3V 20-SOIC

XC18V512SO20I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOIC-20
Contacts	20
Reach Compliance Code	not_compliant
ECCN code	3A991.B.1.A
Maximum access time	15 ns
Maximum clock frequency (fCLK)	33 MHz
Data retention time - minimum	10
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
memory density	524288 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	20
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL/SERIAL
Peak Reflow Temperature (Celsius)	225
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum standby current	0.01 A
Maximum slew rate	0.025 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	7.5 mm
Base Number Matches	1

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XC18V00 Series In-System

Programmable Configuration

PROMs

DS026 (v4.1) December 15, 2003

Product Specification

Features

•

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

- Endurance of 20,000 program/erase cycles

Program/erase over full commercial/industrial

voltage and temperature range (–40°C to +85°C)

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA

Cascadable for storing longer or multiple bitstreams

Low-power advanced CMOS FLASH process

•

Dual configuration modes

Serial Slow/Fast configuration (up to 33 MHz)

- Parallel (up to 264 Mb/s at 33 MHz)

5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals

3.3V or 2.5V output capability

Available in PC20, SO20, PC44, and VQ44 packages

Design support using the Xilinx Alliance and

Foundation series software packages.

JTAG command initiation of standard FPGA

configuration

•

Description

Xilinx introduces the XC18V00 series of in-system program-

mable configuration PROMs (Figure

1).

Devices in this 3.3V

family include a 4-megabit, a 2-megabit, a 1-megabit, and a

512-kilobit PROM that provide an easy-to-use, cost-effec-

tive method for re-programming and storing Xilinx FPGA

configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after CE and OE are enabled, data is available on the

PROM DATA (D0) pin that is connected to the FPGA D

pin. New data is available a short access time after each ris-

ing clock edge. The FPGA generates the appropriate num-

ber of clock pulses to complete the configuration. When the

FPGA is in Slave Serial mode, the PROM and the FPGA

are clocked by an external clock.

CLK CE

When the FPGA is in Master-SelectMAP mode, the FPGA

generates a configuration clock that drives the PROM.

When the FPGA is in Slave-Parallel or Slave-SelectMAP

Mode, an external oscillator generates the configuration

clock that drives the PROM and the FPGA. After CE and

OE are enabled, data is available on the PROMs DATA

(D0-D7) pins. New data is available a short access time

after each rising clock edge. The data is clocked into the

FPGA on the following rising edge of the CCLK. A free-run-

ning oscillator can be used in the Slave-Parallel or

Slave-SelecMAP modes.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC17V00 one-time programmable Serial PROM family.

OE/Reset

TCK

TMS

TDI

TDO

Control

and

JTAG

Interface

Data

Memory

Address

Data

Serial

Parallel

Interface

CEO

D0 DATA

Serial or Parallel Mode

D[1:7]

Parallel Interface

DS026_01_090502

Figure 1:

XC18V00 Series Block Diagram

http://www.xilinx.com/legal.htm.

All other

trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-

ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you

may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any war-

ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS026 (v4.1) December 15, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V512SO20I Related Products

	XC18V512SO20I	XC18V01PC20I	XC18V01SO20I	XC18V01VQ44I	XC18V02PC44I	XC18V02VQ44I	XC18V04PC44I	XC18V04VQ44I	XC18V512PC20I	XC18V512VQ44I
Description	IC PROM SER I-TEMP 3.3V 20-SOIC	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20	IC PROM SER I-TEMP 3.3V 20-SOIC	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44	IC PROM SER I-TEMP 3.3V 44-PLCC	IC PROM SER I-TEMP 3.3V 44-VQFP	IC PROM SER I-TEMP 3.3V 44-PLCC	Configuration Memory, 512KX8, 20ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44	IC PROM SER I-TEMP 3.3V 20-PLCC	IC PROM SER I-TEMP 3.3V 44-VQFP
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	SOIC	QLCC	SOIC	QFP	LCC	QFP	LCC	QFP	QLCC	QFP
package instruction	SOIC-20	PLASTIC, LCC-20	SOIC-20	TQFP, TQFP44,.47SQ,32	PLASTIC, LCC-44	TQFP, TQFP44,.47SQ,32	QCCJ, LDCC44,.7SQ	TQFP, TQFP44,.47SQ,32	PLASTIC, LCC-20	PLASTIC, VQFP-44
Contacts	20	20	20	44	44	44	44	44	20	44
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.B.1.A	3A991.B.1.B.2	3A001.B.1.A	3A991.B.1.B.2	3A001.B.1.A	3A991.B.1.A	3A001.B.1.A	3A991.B.1.B.1	3A991.B.1.B.2	3A991.B.1.A
Maximum access time	15 ns	15 ns	15 ns	15 ns	20 ns	20 ns	20 ns	20 ns	15 ns	15 ns
Maximum clock frequency (fCLK)	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz
Data retention time - minimum	10	10	10	10	10	10	10	10	10	10
Durability	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-G20	S-PQCC-J20	R-PDSO-G20	S-PQFP-G44	S-PQCC-J44	S-PQFP-G44	S-PQCC-J44	S-PQFP-G44	S-PQCC-J20	S-PQFP-G44
length	12.8 mm	8.9662 mm	12.8 mm	10 mm	16.5862 mm	10 mm	16.5862 mm	10 mm	8.9662 mm	10 mm
memory density	524288 bit	1048576 bit	1048576 bit	1048576 bit	2097152 bit	2097152 bit	4194304 bit	4194304 bit	524288 bit	524288 bit
Memory IC Type	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY	CONFIGURATION MEMORY
memory width	8	8	8	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	20	20	20	44	44	44	44	44	20	44
word count	65536 words	131072 words	131072 words	131072 words	262144 words	262144 words	524288 words	524288 words	65536 words	65536 words
character code	64000	128000	128000	128000	256000	256000	512000	512000	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	64KX8	128KX8	128KX8	128KX8	256KX8	256KX8	512KX8	512KX8	64KX8	64KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	QCCJ	SOP	TQFP	QCCJ	TQFP	QCCJ	TQFP	QCCJ	TQFP
Encapsulate equivalent code	SOP20,.4	LDCC20,.4SQ	SOP20,.4	TQFP44,.47SQ,32	LDCC44,.7SQ	TQFP44,.47SQ,32	LDCC44,.7SQ	TQFP44,.47SQ,32	LDCC20,.4SQ	TQFP44,.47SQ,32
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	SMALL OUTLINE	CHIP CARRIER	SMALL OUTLINE	FLATPACK, THIN PROFILE	CHIP CARRIER	FLATPACK, THIN PROFILE	CHIP CARRIER	FLATPACK, THIN PROFILE	CHIP CARRIER	FLATPACK, THIN PROFILE
Parallel/Serial	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL	PARALLEL/SERIAL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.65 mm	4.572 mm	2.65 mm	1.2 mm	4.572 mm	1.2 mm	4.572 mm	1.2 mm	4.572 mm	1.2 mm
Maximum standby current	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
Maximum slew rate	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA	0.025 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	J BEND	GULL WING	GULL WING	J BEND	GULL WING	J BEND	GULL WING	J BEND	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	0.8 mm	1.27 mm	0.8 mm	1.27 mm	0.8 mm	1.27 mm	0.8 mm
Terminal location	DUAL	QUAD	DUAL	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	7.5 mm	8.9662 mm	7.5 mm	10 mm	16.5862 mm	10 mm	16.5862 mm	10 mm	8.9662 mm	10 mm
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0	e0	-
Humidity sensitivity level	3	3	3	3	3	3	3	3	3	-
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225	225	225	-	-
power supply	2.5/3.3,3.3 V	-	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Terminal surface	Tin/Lead (Sn85Pb15)	TIN LEAD	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	-
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30	-	-
Maker	-	-	XILINX	-	XILINX	XILINX	XILINX	-	XILINX	XILINX

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