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Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
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FDPF5N50UT — N-Channel UniFET
TM
Ultra FRFET
TM
MOSFET
November 2013
FDPF5N50UT
500 V, 4 A, 2
Ω
Features
N-Channel UniFET
TM
Ultra FRFET
TM
MOSFET
Description
UniFET
TM
MOSFET is Fairchild Semiconductor’s high voltage
MOSFET family based on planar stripe and DMOS technology.
This MOSFET is tailored to reduce on-state resistance, and to
provide better switching performance and higher avalanche
energy strength. UniFET Ultra FRFET
TM
MOSFET has much
superior body diode reverse recovery performance. Its trr is less
than 50nsec and the reverse dv/dt immunity is 20V/nsec while
normal planar MOSFETs have over 200nsec and 4.5V/nsec
respectively. Therefore UniFET Ultra FRFET MOSFET can
remove additional component and improve system reliability in
certain applications that require performance improvement of the
MOSFET’s body diode. This device family is suitable for
switching power converter applications such as power factor
correction (PFC), flat panel display (FPD) TV power, ATX and
electronic lamp ballasts.
• R
DS(on)
= 1.65
Ω
(Typ.) @ V
GS
= 10 V, I
D
= 2 A
• Low Gate Charge (Typ. 11 nC)
• Low C
rss
(Typ. 5 pF)
• 100% Avalanche Tested
• Improved dv/dt Capability
• RoHS Compliant
Applications
• LCD/LED TV
• Lighting
• Uninterruptible Power Supply
• AC-DC Power Supply
D
G
D
S
G
TO-220F
S
T
C
= 25 C unless otherwise noted.
FDPF5N50UT
500
±30
- Continuous (T
C
= 25 C)
- Continuous (T
C
= 100 C)
- Pulsed
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
(T
C
=
25
o
C)
o
C
o
o
o
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
I
DM
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
Parameter
Unit
V
V
A
A
mJ
A
mJ
V/ns
W
W/
o
C
o
C
o
C
4*
2.4*
16*
216
4
8.5
20
28
0.22
-55 to +150
300
Single Pulsed Avalanche Energy
- Derate above 25
*Drain current limited by maximum junction temperature
[i=s]This post was last edited by qwqwqw2088 on 2020-2-25 08:29[/i]TI Power Management Experimenter Kit TI-PMLK LDO Experimenter Board Cost-Effective Testing Methodology (Rev. A)
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