White Electronic Designs
WSF41632-22XX
PRELIMINARY*
128K
X
32 SRAM & 512Kx32 FLASH MIXED MODULE
FEATURES
Access times of 25ns (SRAM) and 120ns (FLASH)
Packaging
• 66 pin, PGA Type, 1.385" square HIP, hermetic
ceramic HIP (Package 402)
• 68 lead, hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 2). Package to be developed.
128Kx32 SRAM
512Kx32 5V Flash
Organized as 128Kx32 of SRAM and 512Kx32 of
Flash Memory with common data bus
Low power CMOS
Commercial, industrial and military temperature
ranges
TTL compatible inputs and outputs
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Built-in decoupling caps and multiple ground pins
for low noise operation
Weight - 13 grams typical
FLASH MEMORY FEATURES
100,000 erase/program cycles minimum
Sector architecture
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
5V programming; 5V ± 10% supply
Embedded erase and program algorithms
Hardware write protection
Page program operation and internal program
control time.
Note: For programming information refer to flash programming 4M5 application note.
PIN CONFIGURATION FOR WSF41632-22H2X
Top View
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
22
12
FWE
2
#
SWE
2
#
GND
I/O
11
A
10
A
9
A
15
V
CC
FCS#
SCS#
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
FWE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
SWE
1
#
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
SWE
4
#
FWE
4
#
I/O
27
A
4
A
5
A
6
FWE
3
#
SWE
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
66
I/O
0-7
OE#
A
0-18
SCS#
FCS#
Pin Description
D0-31
A0-18
SWE#1-4
SCS#
OE#
VCC
GND
NC
FWE#1-4
FCS
Data Inputs/Outputs
Address Inputs
SRAM Write Enables
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enables
Flash Chip Select
56
Block Diagram
FWE
1
#
SWE
1
#
FWE
2
#
SWE
2
#
FWE
3
#
SWE
3
#
FWE
4
#
SWE
4
#
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WSF41632-22XX
PRELIMINARY
FIGURE 2 – PIN CONFIGURATION FOR WSF41632-22G2TX
Top View
SWE
3
#
SWE
4
#
FWE
1
#
GND
A
6
V
CC
A
10
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
7
A
8
A
9
Pin Description
D0-31
A0-18
SWE#1-4
SCS#
OE#
VCC
GND
NC
FWE#1-4
FCS
Data Inputs/Outputs
Address Inputs
SRAM Write Enables
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enables
Flash Chip Select
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
FCS#
SWE
2
#
FWE
2
#
FWE
3
#
FWE
4
#
SCS#
SWE
1
#
OE#
V
CC
A
12
A
13
A
14
A
15
A
16
NC
A
11
NC
Block Diagram
FWE
1
#
OE#
A
0-18
SCS#
FCS#
SWE
1
#
FWE
2
#
SWE
2
#
FWE
3
#
SWE
3
#
FWE
4
#
SWE
4
#
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
0.940"
The WEDC 68 lead G2T CQFP fills the same fit and function
as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has
the TCE and lead inspection advantage of the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Parameter
Flash Data Retention
20 years
WSF41632-22XX
PRELIMINARY
SRAM TRUTH TABLE
Unit
°C
°C
V
°C
V
SCS#
H
L
L
L
OE#
X
L
H
X
SWE#
X
H
H
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
7.0
150
7.0
NOTE:
1. FCS# must remain high when SCS# is low.
Flash Endurance (write/erase cycles)
100,000 min
Parameter
OE# capacitance
F/S WE
1-4
# capacitance
F/S CS# capacitance
D
0-31
capacitance
A
0-16
capacitance
CAPACITANCE
Ta = +25°C
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Conditions
Max Unit
V
IN
= 0 V, f = 1.0 MHz 80 pF
V
IN
= 0 V, f = 1.0 MHz 30 pF
V
IN
= 0 V, f = 1.0 MHz 50 pF
V
IN
= 0 V, f = 1.0 MHz 30 pF
V
IN
= 0 V, f = 1.0 MHz 80 pF
NOTE:
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
4.5
2.2
-0.5
Max
5.5
V
CC
+ 0.3
+0.8
Unit
V
V
V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 32 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash V
CC
Active Current for Read (1)
Flash V
CC
Active Current for Program or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Output High Voltage
Flash Low V
CC
Lock Out Voltage
Symbol
I
LI
I
LO
I
CCx32
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH1
V
OH2
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
SCS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
SCS# = V
IL
, OE# = FCS# = V
IH
, f = 5MHz, V
CC
= 5.5
FCS# = SCS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
FCS# = V
IL
, OE# = SCS# = V
IH
FCS# = V
IL
, OE# = SCS# = V
IH
I
OL
= 8.0mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
I
OH
= -100 µA, V
CC
= 4.5
Min
Max
10
10
620
80
0.4
260
300
0.45
0.85 x V
CC
V
CC
-0.4
3.2
Unit
µA
µA
mA
mA
V
V
mA
mA
V
V
V
V
2.4
4.2
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
Min
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
25
25
0
25
15
3
0
12
12
-25
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
WSF41632-22XX
PRELIMINARY
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, -55°C
≤
T
A
≤
+125°C
Symbol
Min
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
25
20
20
15
20
3
0
3
15
0
-25
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 2 – AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
V
Z
≈ 1.5V
(Bipolar Supply)
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WSF41632-22XX
PRELIMINARY
FIGURE 3 – SRAM TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
AA
t
RC
ADDRESS
SCS#
t
ACS
t
AA
t
OH
SOE#
t
CHZ
t
CLZ
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OHZ
DATA VALID
READ CYCLE 1, (SCS# = OE# = V
IL
, SWE# = FCS# = V
IH
)
READ CYCLE 2, (SWE# = FCS# = V
IH
)
FIGURE 4 – SRAM WRITE CYCLE - SWE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
SCS#
t
AH
t
AS
SWE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, SWE# CONTROLLED (FCS# = V
IH
)
FIGURE 5 – SRAM WRITE CYCLE - SCS# CONTROLLED
t
WC
ADDRESS
t
AS
SCS#
t
AW
t
CW
t
AH
t
WP
SWE#
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, SCS# CONTROLLED (FCS# = V
IH
)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
京公网安备 11010802033920号
EEWORLD
