WS512K32BV-XXXE
512Kx32 3.3V SRAM MODULE
FEATURES
s
Access Times of 15
†
, 17, 20ns
s
MIL-STD-883 Compliant Devices Available
s
Low Voltage Operation
s
Packaging
• 66-pin, PGA Type, 1.385 inch square Hermetic Ceramic HIP
(Package 402)
• 68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500). Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint
s
Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8
s
Radiation Tolerant with Epitaxial Layer Die
s
s
s
s
s
Commercial, Industrial and Military Temperature Ranges
3.3 Volt Power Supply
BiCMOS
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS512K32BV-XG2XE - 8 grams typical
WS512K32NBV-XH2XE - 13 grams typical
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
†
This speed is Advanced information.
PRELIMINARY*
4
PIN CONFIGURATION FOR WS512K32NBV-XH2XE
TOP VIEW
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
56
SRAM MODULES
PIN DESCRIPTION
I/O
0-31
A
0-18
WE
1-4
CS
1-4
I/O
29
I/O
28
A
0
A
1
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
OE
V
CC
GND
NC
BLOCK DIAGRAM
A
2
WE
1
CS
1
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
I/O
23
I/O
22
OE
A
0-18
512K x 8
512K x 8
512K x 8
512K x 8
I/O
21
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
February 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
PIN CONFIGURATION FOR WS512K32BV-XG2XE
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-18
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
WE
2
WE
3
WE
4
V
CC
OE
CS
2
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
A
17
A
18
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
4
SRAM MODULES
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
WE
1-4
CS
1-4
OE
0.940"
Vcc
GND
The White 68 lead G2 CQFP fills
NC
Not Connected
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
BLOCK DIAGRAM
CQFP form.
WE
1
CS
1
OE
A
0-18
512K x 8
512K x 8
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WS512K32BV-XXXE
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
4.6
150
4.6
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
X
H
L
H
TRUTH TABLE
WE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
3.0
2.2
-0.3
Max
3.6
V
CC
+ 0.3
+0.8
Unit
V
V
V
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G2
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
This parameter is guaranteed by design but not tested.
4
SRAM MODULES
DC CHARACTERISTICS
(V
CC
= 3.3V
±
0.3V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current (x 32 Mode)
Standby Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
Sym
I
LI
I
LO
I
CC
x 32
I
SB
V
OL
V
OH
Conditions
Min
V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, V
CC
= 3.6V
CS = V
IH
, OE = V
IH
, f = 5MHz, V
CC
= 3.6V
I
OL
= 8mA
I
OH
= -4.0mA
2.4
Max
10
10
480
110
0.4
Units
µA
µA
mA
mA
V
V
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
Symbol
Min
15
-15*
Max
Min
17
15
0
15
7
2
0
7
7
2
0
0
-17
Max
Min
20
17
0
17
8
2
0
8
8
-20
Max
Units
ns
20
ns
ns
20
10
ns
ns
ns
ns
10
10
ns
ns
t
OLZ
1
t
CHZ
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
* Advanced information.
4
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Symbol
Min
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
0
15
10
10
8
12
0
0
2
8
0
-15*
Max
Min
17
12
12
9
14
0
0
3
8
0
-17
Max
Min
20
14
14
10
14
0
0
3
9
-20
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
SRAM MODULES
1. This parameter is guaranteed by design but not tested.
* Advanced information.
AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
Output Timing Reference Level
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WS512K32BV-XXXE
TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
4
SRAM MODULES
t
AW
t
CW
t
AH
CS
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
WRITE CYCLE - CS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
AS
t
AW
t
CW
t
AH
CS
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
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