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LTC2230CUP#PBF

Description
IC ADC 10BIT 170MSPS 64-QFN
CategoryAnalog mixed-signal IC    converter   
File Size695KB,32 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
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LTC2230CUP#PBF Overview

IC ADC 10BIT 170MSPS 64-QFN

LTC2230CUP#PBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC64,.35SQ,20
Contacts64
Manufacturer packaging codeUP
Reach Compliance Codecompliant
ECCN code3A991.C.1
Maximum analog input voltage1 V
Minimum analog input voltage-1 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N64
JESD-609 codee3
length9 mm
Maximum linear error (EL)0.0977%
Humidity sensitivity level1
Number of analog input channels1
Number of digits10
Number of functions1
Number of terminals64
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC64,.35SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Sampling rate170 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width9 mm
LTC2230/LTC2231
10-Bit,170Msps/
135Msps ADCs
FEATURES
DESCRIPTIO
Sample Rate: 170Msps/135 Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 890mW/660mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm x 9mm QFN Package
The LTC
®
2230 and LTC2231 are 170Msps/135Msps, sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15ps
RMS
allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include
±0.2LSB
INL (typ),
±0.1LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.12LSB
RMS
.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
APPLICATIO S
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V
DD
0.5V
TO 3.6V
90
85
80
OV
DD
SFDR (dBFS)
+
ANALOG
INPUT
INPUT
S/H
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D9
D0
CMOS
OR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
22301 TA01
ENCODE INPUT
U
SFDR vs Input Frequency
4th OR HIGHER
75
70
65
60
55
50
45
40
0
100
300
500
200
400
INPUT FREQUENCY (MHz)
600
2nd OR 3rd
2230 TA01b
U
U
22301fb
1

LTC2230CUP#PBF Related Products

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Description IC ADC 10BIT 170MSPS 64-QFN IC ADC 10BIT 135MSPS 64-QFN IC ADC 10BIT 135MSPS 64-QFN IC ADC 10BIT 170MSPS 64-QFN IC ADC 10BIT 170MSPS 64-QFN IC ADC 10BIT 135MSPS 64-QFN IC ADC 10BIT 170MSPS 64-QFN IC ADC 10BIT 135MSPS 64-QFN
Brand Name Linear Technology Linear Technology Linear Technology Linear Technology Linear Technology Linear Technology Linear Technology Linear Technology
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to
Maker Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI )
Parts packaging code QFN QFN QFN QFN QFN QFN QFN QFN
package instruction HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20 HVQCCN, LCC64,.35SQ,20
Contacts 64 64 64 64 64 64 64 64
Manufacturer packaging code UP UP UP UP UP UP UP UP
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN code 3A991.C.1 3A991.C.1 3A991.C.1 3A991.C.1 3A991.C.1 3A991.C.1 3A991.C.1 3A991.C.1
Maximum analog input voltage 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 V
Minimum analog input voltage -1 V -1 V -1 V -1 V -1 V -1 V -1 V -1 V
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 code S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64
JESD-609 code e3 e3 e3 e3 e3 e3 e3 e3
length 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm
Maximum linear error (EL) 0.0977% 0.0781% 0.0781% 0.0977% 0.0977% 0.0781% 0.0977% 0.0781%
Humidity sensitivity level 1 1 1 1 1 1 1 1
Number of analog input channels 1 1 1 1 1 1 1 1
Number of digits 10 10 10 10 10 10 10 10
Number of functions 1 1 1 1 1 1 1 1
Number of terminals 64 64 64 64 64 64 64 64
Maximum operating temperature 70 °C 85 °C 70 °C 85 °C 85 °C 70 °C 70 °C 85 °C
Output bit code OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY
Output format PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN
Encapsulate equivalent code LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20 LCC64,.35SQ,20
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260 260 260 260 260 260
power supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Sampling rate 170 MHz 135 MHz 135 MHz 170 MHz 170 MHz 135 MHz 170 MHz 135 MHz
Sample and hold/Track and hold SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
Maximum seat height 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Nominal supply voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature 30 30 30 30 30 30 30 30
width 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm
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