W3EG7263S202D3 datasheet, PDF - EEWORLD Datasheet

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W3EG7263S202D3: Description512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL; Categorystorage storage; File Size256KB，13 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W3EG7263S202D3 Overview

512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL

W3EG7263S202D3 Parametric

Parameter Name	Attribute value
Maker	White Electronic Designs Corporation
package instruction	DIMM,
Reach Compliance Code	unknown
access mode	FOUR BANK PAGE BURST
Maximum access time	0.8 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N184
memory density	4831838208 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	DUAL

W3EG7263S202D3 Preview

White Electronic Designs

W3EG7263S-D3

-JD3

-AJD3

PRELIMINARY*

512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL

FEATURES

Double-data-rate architecture

Clock Speeds: 100MHz, 133MHz and 166MHz

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2,5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Serial presence detect

Power supply: V

: 2.5V ± 0.2V

JEDEC standard 184 pin DIMM package

•

Package height options:

JD3: 30.48mm (1.20") and

AJD3: 28.70mm (1.13")

This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

DESCRIPTION

The W3EG7263S is a 64Mx72 Double Data Rate

SDRAM memory module based on 256Mb DDR SDRAM

component. The module consists of eighteen 64Mx4 DDR

SDRAMs in 66 pin TSOP package mounted on a 184 Pin

FR4 substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lenths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

OPERATING FREQUENCIES

DDR333 @CL=2.5

Clock Speed

CL-t

RCD

-t

166MHz

2.5-3-3

DDR266 @CL=2

133MHz

2-2-2

DDR266 @CL=2

133MHz

2-3-3

DDR266 @CL=2.5

133MHz

2.5-3-3

DDR200 @CL=2

100MHz

2-2-2

April 2004

Rev. # 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

PIN CONFIGURATION

SYMBOL

REF

DQ0

DQ1

DQS0

DQ2

DQ3

RESET#

DQ8

DQ9

DQS1

CCQ

DQ10

DQ11

CKE0

CCQ

DQ16

DQ17

DQS2

DQ18

CCQ

DQ19

DQ24

DQ25

DQS3

DQ26

DQ27

CB0

CB1

SYMBOL

DQS8

CB2

CB3

BA1

DQ32

CCQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

CCQ

WE#

DQ41

CAS#

DQS5

DQ42

DQ43

DQ48

DQ49

CCQ

DQS6

DQ50

DQ51

CCID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

SYMBOL

DQ4

DQ5

CCQ

DQS9

DQ6

DQ7

CCQ

DQ12

DQ13

DQS10

DQ14

DQ15

CCQ

DQ20

A12

DQ21

A11

DQS11

DQ22

DQ23

DQ28

DQ29

CCQ

DQS12

DQ30

DQ31

CB4

CB5

CCQ

CK0

CK0#

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

SYMBOL

DQS17

A10

CB6

CCQ

CB7

DQ36

DQ37

DQS13

DQ38

DQ39

DQ44

RAS#

DQ45

CCQ

CS0#

DQS14

DQ46

DQ47

CCQ

DQ52

DQ53

DQS15

DQ54

DQ55

CCQ

DQ60

DQ61

DQS16

DQ62

DQ63

CCQ

SA0

SA1

SA2

CCSPD

A0-A12

BA0-BA1

DQ0-DQ63

CB0-CB7

DQS0-DQS17

CK0

CK0#

CKE0

CS0#

RAS#

CAS#

WE#

CCQ

REF

CCSPD

SDA

SCL

SA0-SA2

CCID

RESET#

W3EG7263S-D3

-JD3

-AJD3

PRELIMINARY

PIN NAMES

Address input (Multiplexed)

Bank Select Address

Data Input/Output

Check bits

Data Strobe Input/Output

Clock Input

Clock Enable input

Chip Select Input

Row Address Strobe

Column Address Strobe

Write Enable

Power Supply (2.5V)

Power Supply for DQS (2.5V)

Ground

Power Supply for Reference

Serial EEPROM Power Supply

(2.3V to 3.6V)

Serial data I/O

Serial clock

Address in EEPROM

Indentiﬁcation Flag

No Connect

Reset Enable

April 2004

Rev. # 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FUNCTIONAL BLOCK DIAGRAM

VSS

RS0A#

DQS0

DQ0

DQ1

DQ2

DQ3

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQ4

DQ5

DQ6

DQ7

W3EG7263S-D3

-JD3

-AJD3

PRELIMINARY

DQS9

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS1

DQ8

DQ9

DQ10

DQ11

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS10

DQ12

DQ13

DQ14

DQ15

DQS

I/O3

I/O2

I/O1

I/O0

CS#

D10

DQS2

DQ16

DQ17

DQ18

DQ19

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS11

DQ20

DQ21

DQ22

DQ23

DQS

I/O3

I/O2

I/O1

I/O0

CS#

D11

DQS3

DQ24

DQ25

DQ26

DQ27

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS12

DQ28

DQ29

DQ30

DQ31

DQS

I/O3

I/O2

I/O1

I/O0

CS#

D12

DQS4

DQ32

DQ33

DQ34

DQ35

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS13

DQ36

DQ37

DQ38

DQ39

DQS

I/O3

I/O2

I/O1

I/O0

CS#

CK0

SDRAM

D13

PLL

CK0#

DQS5

DQ40

DQ41

DQ42

DQ43

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS14

DQ44

DQ45

DQ46

DQ47

DQS

I/O3

I/O2

I/O1

I/O0

CS#

D14

DQS6

DQS15

DQ48

DQ49

DQ50

DQ51

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQ52

DQ53

DQ54

DQ55

DQS

I/O3

I/O2

I/O1

I/O0

CS#

Serial PD

SCL

SA1

SA2

SDA

D15

DQS7

DQ56

DQ57

DQ58

DQ59

DQS

I/O3

I/O2

I/O1

I/O0

CS#

DQS16

DQ60

DQ61

DQ62

DQ63

DQS

I/O3

I/O2

I/O1

I/O0

CS#

SA0

D16

CCSPD

CCQ

SPD

D0 - D17

DQS8

DQS17

DQ56

DQ57

DQ58

DQ59

DQS

I/O3

I/O2

I/O1

I/O0

CS#

CB4

CB5

CB6

CB7

DQS

I/O3

I/O2

I/O1

I/O0

CS#

D17

REF

D0 - D17

CS0#

BA0-BA1

A0-A12

RAS#

CAS#

CKE0

WE#

PCK

PCK#

RS0A#

RS0B#

RBA0 - RBA1

RA0 - RA12

RRAS#

RCAS

RCKE0A

RCKE0B

RWE#

RESET#

BA0-BA1: SDRAMs DQ0-D17

A0-A12: SDRAMs DQ0-D17

RAS#: SDRAMs DQ0-D17

CAS#: SDRAMs DQ0-D17

CKE: SDRAMs DQ0-D8

CKE: SDRAMs DQ9-D17

WE#: SDRAMs DQ0-D17

Notes:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQSresistors: 22 Ohms

April 2004

Rev. # 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage Temperature

Power Dissipation

Short Circuit Current

Symbol

, V

OUT

, V

CCQ

STG

Value

-0.5 - 3.6

-1.0 - 3.6

-55 - +150

W3EG7263S-D3

-JD3

-AJD3

PRELIMINARY

Units

°C

Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C

70°C, V

= 2.5V ± 0.2V

Parameter

Supply Voltage

Reference Voltage

Termination Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Symbol

CCQ

REF

Min

2.3

1.15

REF

+ 0.15

-0.3

+ 0.76

—

Max

2.7

1.35

CCQ

+ 0.3

REF

- 0.15

—

- 0.76

Unit

CAPACITANCE

TA = 25°C, f = 1MHz, V

= 2.5V

Parameter

Input Capacitance (A0-A12)

Input Capacitance (RAS#, CAS#, WE#)

Input Capacitance (CKE0)

Input Capacitance (CK0,CK0#)

Input Capacitance (CS0#)

Input Capacitance (DQM0-DQM8)

Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)

Data input/output capacitance (CB0-CB7)

Symbol

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

Min

—

Max

6.5

5.5

6.5

Unit

April 2004

Rev. # 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

SPECIFICATIONS AND TEST CONDITIONS

W3EG7263S-D3

-JD3

-AJD3

PRELIMINARY

Recommended operating conditions, 0°C

+70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V.

Includes DDR SDRAM components and PLL and Register

Rank 1

Conditions

One device bank; Active - Precharge;

= t

(MIN); t

= t

(MIN); DQ,DM

and DQS inputs changing once per

clock cycle; Address and control inputs

changing once every two cycles.

One device bank; Active-Read-

Precharge Burst = 2; t

= t

(MIN);

= t

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per

clock cycle.

All device banks idle; Power-down

mode; t

= t

(MIN); CKE = (low)

CS# = High; All device banks idle;

= t

(MIN); CKE = High; Address

and other control inputs changing once

per clock cycle. V

= V

REF

for DQ, DQS

and DM.

One device bank active; Power-Down

mode; t

(MIN); CKE = (low)

CS# = High; CKE = High; One device

bank; Active-Precharge;t

= t

RAS

(MAX); t

= t

(MIN); DQ, DM and

DQS inputs changing twice per clock

cycle; Address and other control inputs

changing once per clock cycle.

Burst = 2; Reads; Continuous burst;

One device bank active; Address and

control inputs changing once per clock

cycle; t

= t

(MIN); l

OUT

= 0mA.

Burst = 2; Writes; Continuous burst;

One device bank active; Address and

control inputs changing once per clock

cycle; t

= t

(MIN); DQ,DM and DQS

inputs changing once per clock cycle.

= t

(MIN)

CKE

0.2V

Four bank interleaving Reads (BL=4)

with auto precharge with t

(MIN);

(MIN); Address and control

inputs change only during Active Read

or Write commands.

DDR333@CL=2.5

Max

TBD

DDR266:@CL=2, 2.5

Max

1715

DDR200@CL=2 S

Max

1715

Rank 2

Standby

State

DD3N

Parameter

Operating Current

Symbol

DD0

Units

Operating Current

DD1

TBD

2255

DD3N

Precharge Power-

Down Standby Current

Idle Standby Current

DD2P

DD2F

TBD

671

rnA

DD2P

DD2F

Active Power-Down

Standby Current

Active Standby Current

DD3P

DD3N

TBD

540

1121

540

1121

DD3P

DD3N

Operating Current

DD4R

TBD

2795

DD3N

Operating Current

DD4W

TBD

2795

rnA

DD3N

Auto Refresh Current

Self Refresh Current

Operating Current

DD5

DD6

DD7A

TBD

3281

365

5315

3281

365

5315

DD3N

DD6

DD3N

April 2004

Rev. # 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3EG7263S202D3 Related Products

	W3EG7263S202D3	W3EG7263S-D3	W3EG7263S335JD3	W3EG7263S335AJD3	W3EG7263S202JD3	W3EG7263S-JD3	W3EG7263S-AJD3	W3EG7263S202AJD3
Description	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL	512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL
Maker	White Electronic Designs Corporation	-	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	-	-	White Electronic Designs Corporation
package instruction	DIMM,	-	DIMM,	DIMM,	DIMM,	-	-	DIMM,
Reach Compliance Code	unknown	-	unknow	unknow	unknow	-	-	unknown
access mode	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	-	FOUR BANK PAGE BURST
Maximum access time	0.8 ns	-	0.7 ns	0.7 ns	0.8 ns	-	-	0.8 ns
Other features	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	-	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N184	-	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	-	-	R-XDMA-N184
memory density	4831838208 bit	-	4831838208 bi	4831838208 bi	4831838208 bi	-	-	4831838208 bit
Memory IC Type	DDR DRAM MODULE	-	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	-	-	DDR DRAM MODULE
memory width	72	-	72	72	72	-	-	72
Number of functions	1	-	1	1	1	-	-	1
Number of ports	1	-	1	1	1	-	-	1
Number of terminals	184	-	184	184	184	-	-	184
word count	67108864 words	-	67108864 words	67108864 words	67108864 words	-	-	67108864 words
character code	64000000	-	64000000	64000000	64000000	-	-	64000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	-	SYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	70 °C	70 °C	-	-	70 °C
organize	64MX72	-	64MX72	64MX72	64MX72	-	-	64MX72
Package body material	UNSPECIFIED	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	-	-	UNSPECIFIED
encapsulated code	DIMM	-	DIMM	DIMM	DIMM	-	-	DIMM
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	-	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	-	-	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	-	-	Not Qualified
self refresh	YES	-	YES	YES	YES	-	-	YES
Maximum supply voltage (Vsup)	2.7 V	-	2.7 V	2.7 V	2.7 V	-	-	2.7 V
Minimum supply voltage (Vsup)	2.3 V	-	2.3 V	2.3 V	2.3 V	-	-	2.3 V
Nominal supply voltage (Vsup)	2.5 V	-	2.5 V	2.5 V	2.5 V	-	-	2.5 V
surface mount	NO	-	NO	NO	NO	-	-	NO
technology	CMOS	-	CMOS	CMOS	CMOS	-	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	-	COMMERCIAL
Terminal form	NO LEAD	-	NO LEAD	NO LEAD	NO LEAD	-	-	NO LEAD
Terminal location	DUAL	-	DUAL	DUAL	DUAL	-	-	DUAL

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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