A3922
Automotive, Full-Bridge MOSFET Driver
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FEATURES AND BENEFITS
Full-bridge MOSFET Driver
Bootstrap gate drive for N-channel MOSFET bridge
Cross-conduction protection with adjustable dead time
Charge pump for low supply voltage operation
Programmable gate drive voltage
5.5 to 50 V supply voltage operating range
Integrated current sense amplifier
SPI compatible serial interface
Bridge control by direct logic inputs or serial interface
TTL-compatible logic inputs
Open-load detection
Extensive programmable diagnostics
Diagnostic verification
Safety-assist features
DESCRIPTION
The A3922 is an N-channel power MOSFET driver capable of
controlling MOSFETs connected in a full-bridge (H-bridge)
arrangement and is specifically designed for automotive
applications with high-power inductive loads, such as brush
DC motors solenoids and actuators.
A unique charge pump regulator provides a programmable gate
drive voltage for battery voltages down to 7 V and allows the
A3922 to operate with a reduced gate drive, down to 5.5 V.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs.
The full bridge can be controlled by independent logic level
inputs or through the SPI-compatible serial interface. The
external power MOSFETs are protected from shoot-through
by programmable dead time.
Integrated diagnostics provide indication of multiple internal
faults, system faults, and power bridge faults, and can be
configured to protect the power MOSFETs under most short-
circuit conditions. For safety-critical systems, the integrated
diagnostic operation can be verified under control of the serial
interface.
In addition to providing full access to the bridge control, the
serial interface is also used to alter programmable settings such
as dead time, V
DS
threshold, and fault blank time. Detailed
diagnostic information can be read through the serial interface.
Package: 28-Pin eTSSOP (suffix LP)
Not to scale
-
2
The A3922 is supplied in a 28-pin eTSSOP (suffix ‘LP’). This
package is available in lead (Pb) free versions, with 100%
matte-tin leadframe plating (suffix –T).
VBAT
ECU
SPI
A3922
GND
Typical Application – Functional Block Diagram
A3922-DS
A3922
Automotive, Full-Bridge MOSFET Driver
Selection Guide
Part Number
A3922KLPTR-T
*Contact Allegro
™
for additional packing options.
Packing
4000 pieces per reel
Package
9.7 mm × 4.4 mm, 1.2 mm nominal height
28-lead eTSSOP with exposed thermal pad
Table of Contents
Features and Benefits
Specifications
1
3
Serial Interface
Serial Registers Definition
Configuration Registers
Verification Registers
Diagnostic Registers
Control Register
Status Register
Config 0, 1
Config 2, 3
Config 4, 5
Verify Command 0, 1
Verify Result 0, 1
Mask 0, 1
Diag 0, 1, 2
Control
Status
33
33
34
35
35
35
36
37
38
39
41
42
43
44
45
46
47
48
49
49
49
50
50
50
Functional Description
Absolute Maximum Ratings
Thermal Characteristics
Pinout Diagram and Terminal List Table
Functional Block Diagram
Electrical Characteristics Table
Overcurrent Fault Timing Diagrams
VDS Fault Timing Diagrams
Logic Truth Tables
Input and Output Terminal Functions
Power Supplies
Gate Drives
Logic Control Inputs
Output Disable
Sleep Mode
Current Sense Amplifier
Diagnostic Monitors
Status and Diagnostic Registers
Chip-Level Protection
Operational Monitors
Power Bridge and Load Faults
Fault Action
Fault Masks
Diagnostic and System Verification
On-Line Verification
Off-Line Verification
15
15
16
16
18
19
19
20
20
20
20
21
23
27
28
28
29
30
3
3
4
5
6
12
13
14
Serial Register Reference
37
Applications Information
Input / Output Structures
Package Drawing
Power Bridge PWM Control
Current Sense Amplifier Configuration
Dead Time Selection
Bootstrap Capacitor Selection
Bootstrap Charging
VREG Capacitor Selection
Supply Decoupling
Braking
47
51
52
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3922
Automotive, Full-Bridge MOSFET Driver
SPECIFICATIONS
Absolute Maximum Ratings
1, 2
Characteristic
Load Supply Voltage
Pumped Regulator Terminal
Charge Pump Capacitor Low Terminal
Charge Pump Capacitor High Terminal
Battery Compliant Logic Input
Terminals
Logic Input Terminals
Logic Output Terminals
Sense Amplifier Input
Sense Amplifier Output
Bridge Drain Monitor Terminals
Bootstrap Supply Terminals
High-Side Gate Drive Output
Terminals
Motor Phase Terminals
Low-Side Gate Drive Output Terminals
Bridge Low-Side Source Terminal
Operating Ambient Temperature
Maximum Junction Temperature
Transient Junction Temperature
Storage Temperature
1
With
2
Lowercase
Symbol
V
BB
V
REG
V
CP1
V
CP2
V
IB
V
I
V
O
V
CSI
V
CSO
V
BRG
V
CX
V
GHX
V
SX
V
GLX
V
LSS
T
A
T
J(max)
T
Jt
T
stg
VREG
CP1
CP2
Notes
Rating
–0.3 to 50
–0.3 to 16
–0.3 to 16
V
CP1
– 0.3 to V
REG
+ 0.3
–0.3 to 50
–0.3 to 6
–0.3 to 6
–4 to 6.5
–0.3 to V
DD
+ 0.3
–5 to 55
–0.3 to V
REG
+ 50
V
CX
– 16 to V
CX
+ 0.3
V
CX
– 16 to V
CX
+ 0.3
V
REG
– 16 to 16
V
REG
– 16 to 18
–40 to 150
165
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ºC
ºC
ºC
ºC
HA, HBn, LAn, LB, RESETn, ENABLE
STRn, SCK, SDI
SDO
CSP, CSM
CSO
VBRG
CA, CB
GHA, GHB
SA, SB
GLA, GLB
LSS
Limited by power dissipation
Overtemperature event not exceeding 10 seconds,
lifetime duration not exceeding 10 hours,
guaranteed by design characterization.
180
–55 to 150
respect to GND. Ratings apply when no other circuit operating constraints are present.
“x” in pin names and symbols indicates a variable sequence character.
Thermal Characteristics:
May require derating at maximum conditions; see Power Derating section
Characteristic
Symbol
R
θJA
R
θJP
*Additional thermal information available on the Allegro website.
Test Conditions*
4-layer PCB based on JEDEC standard
2-layer PCB with 3.8 in
2
copper each side
Value
28
38
2
Unit
ºC/W
ºC/W
ºC/W
Package Thermal Resistance
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3922
Automotive, Full-Bridge MOSFET Driver
Pinout Diagram and Terminal List Table
CP2
VBB
VBRG
ENABLE
RESETn
HA
LAn
HBn
LB
GND
SDI
STRn
SDO
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PAD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CP1
VREG
CA
GHA
SA
CB
GHB
SB
GLA
LSS
GLB
CSP
CSM
CSO
Package LP, 28-Pin eTSSOP Pinout Diagram
Terminal List Table
Terminal
Name
VBB
ENABLE
VREG
CP1
CP2
GND
RESETn
SDI
SCK
STRn
SDO
CSP
CSM
CSO
HA
Terminal
Number
2
4
27
28
1
10
5
11
14
12
13
17
16
15
6
Terminal Description
Main power supply
Output enable
Gate drive supply output
Pump capacitor
Pump capacitor
Digital ground
Standby mode control
Serial data input
Serial clock input
Serial strobe (chip select) input
Serial data output
Current sense amp + input
Current sense amp – input
Current sense amp output
Phase A HS control
Terminal
Name
HBn
LAn
LB
VBRG
CA
GHA
SA
GLA
CB
GHB
SB
GLB
LSS
PAD
Terminal
Number
8
7
9
3
26
25
24
20
23
22
21
18
19
–
Terminal Description
Phase B HS control
Phase A LS control
Phase B LS control
High-side drain voltage sense
Phase A bootstrap capacitor
Phase A high-side gate drive
Phase A motor connection
Phase A low-side gate drive
Phase B bootstrap capacitor
Phase B high-side gate drive
Phase B motor connection
Phase B low-side gate drive
Low-side source
Thermal pad; connect to GND
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3922
Automotive, Full-Bridge MOSFET Driver
C
P
CP1
CP2
VBB
VREG
Logic Supply
Regulator
V
DL
Charge
Pump
ENABLE
Bootstrap
Monitor
VREG
LS
Drive
Phase A
LSS
LB
As above for
Phase B
RESETn
CB
C
BOOTB
GHB
SB
GLB
HS
Drive
VDS
Monitor
VDS
Monitor
GLA
R
GLA
R
GLB
GHA
R
GHA
SA
R
GHB
Charge
Pump
Regulator
VBRG
CA
C
BOOTA
C
REG
VBAT
HA
LAn
HBn
Control
Logic
Timers
STRn
SCK
SDI
SDO
Serial
Interface
Diagnostics &
Protection
Diagnostic
Verification
*V
DAC
= V
OLTON
& V
OCT
GND
DAC
DAC
V
OOS
V
DAC
*
CSM
CSO
Sense
Amp
CSP
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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