XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
AUGUST 2009
REV. 1.0.1
GENERAL DESCRIPTION
The XR16M781
1
(M781) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
a VLIO bus interface and has 64 bytes of transmit
and receive FIFOs, programmable transmit and
receive FIFO trigger levels, automatic hardware and
software flow control, and data rates of up to 20 Mbps
at 3.3V, 16 Mbps at 2.5V and 10 Mbps at 1.8V with
4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M781 can be minmized by enabling the sleep mode
and PowerSave mode.
The M781 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M781 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
VLIO bus interface
•
Pin-to-pin compatible with SC16C850V and
SC16C850SV in 32-QFN package
•
20 Mbps maximum data rate
•
Programmable TX/RX FIFO Trigger Levels
•
TX/RX FIFO Level Counters
•
Independent TX/RX Baud Rate Generator
•
Fractional Baud Rate Generator
•
Auto RTS/CTS Hardware Flow Control
•
Auto XON/XOFF Software Flow Control
•
Auto RS-485 Half-Duplex Direction Control
•
Multidrop mode w/ Auto Address Detect
•
Sleep Mode with Automatic Wake-up
•
PowerSave mode
•
Infrared (IrDA 1.0 and 1.1) mode
•
1.62V to 3.63V supply operation
•
Crystal oscillator or external clock input
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
F
IGURE
1. XR16M781 B
LOCK
D
IAGRAM
VCC
(1.62 to 3.63 V)
TX
BRG
UART
GND
64 Byte TX FIFO
TX &
IR
ENDEC RX
64 Byte RX FIFO
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
Pw rSave
LLA#
AD7:AD0
IOR#
IOW #
CS#
INT
RESET#
VLIO Bus
Interface
Regs
RX
BRG
Crystal Osc/Buffer
XTAL1
XTAL2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
REV. 1.0.1
RESET#
CTS#
RESET#
DTR#
RTS#
INT
CTS#
RTS#
LLA#
INT
NC
18 17 16 15 14 13
VCC 19
12
AD0 20
11
AD1 21
AD2 22
AD3 23
AD4 24
1
AD5
2
AD6
3
AD7
4
RX
5
TX
24-pin QFN
10
9
8
7
6
CS#
24 23 22 21 20 19 18 17
IOR#
GND
IOW#
XTAL2
XTAL1
PWRSAVE
LLA#
NC
NC
16
15
14
13
12
11
10
9
CS
NC
NC
IOR#
GND
IOW#
XTAL2
XTAL1
PWRSAVE
DSR#
CD#
RI#
VCC
AD0
AD1
AD2
AD3
25
26
27
28
29
30
31
32
AD4
32-pin QFN
1 2 3 4 5 6 7 8
NC
AD5
AD6
AD7
RX
TX
A1 Corner
1 2
A
B
C
D
E
Transparent Top View
CTS#
VCC
AD0
AD3
AD4
RESET#
AD5
AD7
AD1
AD2
RTS#
DTR#
RX
CS#
AD6
LLA#
INT
DSR#
PWRSAVE
TX
IOR#
GND
XTAL2
XTAL1
IOW#
3 4
5
ORDERING INFORMATION
P
ART
N
UMBER
XR16M781IL24
XR16M781IL32
XR16M781IB25
P
ACKAGE
24-Pin QFN
32-Pin QFN
25-Pin BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
2
XR16M781
REV. 1.0.1
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
PIN DESCRIPTIONS
Pin Description
N
AME
24-QFN
P
IN
#
32-QFN
PIN#
25-BGA
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
IOR#
20
21
22
23
24
1
2
3
12
29
30
31
32
1
3
4
5
14
C1
D2
E2
D1
E1
B2
E3
C2
A5
I/O
Multiplexed Address/Data lines [7:0]. The register address is
latched on the rising edge of the LLA#. After the LLA# signal goes
high, the UART enters the data phase where the data is placed on
these lines.
I
Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
Interrupt output (active high). The output state is defined by the
user through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
IOW#
10
12
E5
I
CS#
6
8
D3
I
LLA#
14
19
A4
I
INT
15
20
B4
O
MODEM OR SERIAL I/O INTERFACE
TX
5
7
E4
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6]. This pin can also be used as the
Auto RS-485 Half-duplex Direction control output, see FCTR[3] and
EMSR[3].
RX
4
6
C3
I
RTS#
16
21
A3
O
3
XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
Pin Description
N
AME
CTS#
24-QFN
P
IN
#
18
32-QFN
PIN#
24
25-BGA
P
IN
#
A1
T
YPE
I
D
ESCRIPTION
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
UART Data-Terminal-Ready (active low) or general purpose output.
UART Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used.
REV. 1.0.1
DTR#
DSR#
CD#
RI#
-
-
-
-
22
25
26
27
B3
C4
-
-
O
I
I
I
ANCILLARY SIGNALS
XTAL1
XTAL2
PwrSave
8
9
7
10
11
9
D5
C5
D4
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the M781’s data bus
interface from the host preventing other bus activities that cause
higher power drain during sleep mode. See Sleep Mode with Auto
Wake-up and Power-Save Feature section for details. This pin does
not have an internal pull-down resistor. This input should be con-
nected to GND when not used.
Device reset (active low). A 40 ns minimum LOW pulse on this pin
will reset the internal registers and all outputs of the UART. The
UART transmitter output will be held HIGH, the receiver input will
be ignored and outputs are reset during reset period (see UART
Reset Conditions).
1.62V to 3.63V power supply.
Power supply common, ground.
The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
No Connects.
RESET#
17
23
A2
O
VCC
GND
GND
19
11
Center
Pad
28
13
Center
Pad
B1
B5
-
Pwr
Pwr
Pwr
NC
13
2, 15-18
-
-
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
4
XR16M781
REV. 1.0.1
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
1.0 PRODUCT DESCRIPTION
The XR16M781 (M781) is a high performance single-channel UART with a VLIO bus interface. It has its set of
device configuration registers. The configuration registers set is 16550 UART compatible for control, status
and data transfer. Additionally, the M781 channel has 64 bytes of transmit and receive FIFOs, Automatic RTS/
CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared
encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of
divide by 1 or 4, and data rate up to 20 Mbps. The XR16M781 can operate from 1.62 to 3.63 volts. The M781
is fabricated with an advanced CMOS process.
Larger FIFO
The M781 provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes
in the XR16L580. The M781 is designed to work with high performance data communication systems, that
requires fast data processing time. Increased performance is realized in the M781 by the larger transmit and
receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external
processor to handle more networking tasks within a given time. For example, the XR16L580 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 64 byte FIFO in the M781, the data buffer will not require unloading/loading for 6.1
ms. This increases the service interval giving the external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt
and automatic hardware/software flow control is uniquely provided for maximum data throughput performance
especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s
bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The M781 is capable of operation up to 20 Mbps at 3.3V with 4X internal sampling clock rate. The device can
operate at 3.3V with a 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 80 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit and
sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the M781 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/
decoder, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. The M781 includes new features
such as 9-bit (Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX,
fast IR mode and fractional baud rate generator.
5
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