TC7WPN3125FK/FC
TOSHIBA Digital Integrated Circuit
Silicon Monolithic
TC7WPN3125FK, TC7WPN3125FC
Low Voltage/Low Power 2-Bit Dual Supply Bus Buffer
The TC7WPN3125 is a dual supply, advanced high-speed
CMOS 2-bit dual supply voltage interface bus buffer fabricated
with silicon gate CMOS technology.
It is also designed with over voltage tolerant inputs and
outputs up to 3.6 V.
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,
or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V,
1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus,
the B-output with the 1.8-V, 2.5-V, 3.3-V bus.
The enable input (
OE
) can be used to disable the device so
that the signal lines are effectively isolated.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC7WPN3125FK
TC7WPN3125FC
Weight:
SSOP8-P-0.50A : 0.01 g (typ.)
CSON8-P-0.4 : 0.002 g (typ.)
Features
•
•
Level converter for interfacing 1.2-V to 1.8-V, 1.2-V to 2.5-V, 1.2-V to 3.3-V, 1.5-V to 2.5-V, 1.5-V to 3.3-V, 1.8-V
to 2.5-V, 1.8-V to 3.3-V or 2.5 V to 3.3-V system.
High-speed operation : t
pd
= 13.7 ns (max) (V
CCA
=
2.5
±
0.2 V, V
CCB
=
3.3
±
0.3 V)
t
pd
= 14.8 ns (max) (V
CCA
=
1.8
±
0.15 V, V
CCB
=
3.3
±
0.3 V)
t
pd
= 16.0 ns (max) (V
CCA
=
1.5
±
0.1 V, V
CCB
=
3.3
±
0.3 V)
t
pd
= 29 ns (max) (V
CCA
=
1.2
±
0.1 V, V
CCB
=
3.3
±
0.3 V)
t
pd
= 18.5 ns (max) (V
CCA
=
1.8
±
0.15 V, V
CCB
=
2.5
±
0.2 V)
t
pd
= 19.7 ns (max) (V
CCA
=
1.5
±
0.15 V, V
CCB
=
2.5
±
0.2 V)
t
pd
= 33 ns (max) (V
CCA
=
1.2
±
0.15 V, V
CCB
=
2.5
±
0.2 V)
t
pd
= 43 ns (max) (V
CCA
=
1.2
±
0.1 V, V
CCB
=
1.8
±
0.15 V)
Output current : I
OH
/ I
OL
= ±3
mA (min) (V
CC
=
3.0 V)
I
OH
/ I
OL
= ±2mA
(min) (V
CC
=
2.3 V)
I
OH
/ I
OL
= ±0.5
mA (min) (V
CC
=
1.65 V)
Latch-up performance:
-300
mA
ESD performance: Machine model
≥ ±200
V
Human body model
≥ ±2000
V
Ultra-small package: CSON8(CST8), SSOP8(US8)
Low current consumption : Using the new circuit significantly reduces current consumption when
OE
= “H”.
Suitable for battery-driven applications such as PDAs and cellular phones.
3.6-V tolerant function and power-down protection provided on all inputs and outputs.
•
•
•
•
•
•
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
Start of commercial production
2005-09
1
2014-03-01
TC7WPN3125FK/FC
Absolute Maximum Ratings
(Note 1)
Characteristics
Power supply voltage
DC input voltage
(An, OE )
(Note 2)
Symbol
V
CCA
V
CCB
V
IN
V
OUT
I
IK
I
OK
I
OUTB
I
CCA
I
CCB
P
D
T
stg
Rating
−
0.5 to 4.6
−
0.5 to 4.6
−
0.5 to 4.6
−
0.5 to 4.6
−
50
±
50
±
6
±
25
±
50
Unit
V
V
(Note 3)
V
mA
(Note 5)
mA
mA
mA
mW
°
C
DC output voltage
(Bn)
Input diode current
Output diode current
DC output current
DC V
CC
/ground current per supply pin
Power dissipation
Storage temperature
−
0.5 to V
CCB
+
0.5 (Note 4)
200 (SSOP8)
150 (CSON8)
−
65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: Don’t supply a voltage to V
CCB
pin when V
CCA
is in the OFF state.
Note 3: Output in OFF state
Note 4: High or Low state. I
OUT
absolute maximum rating must be observed.
Note 5: V
OUT
<
GND, V
OUT
>
V
CC
Operating Ranges
(Note 1)
Characteristics
Power supply voltage
(Note 2)
Input voltage
Output voltage
(Bn)
Output current
(Bn)
Operating temperature
Input rise and fall time
(An, OE )
Symbol
V
CCA
V
CCB
V
IN
V
OUTB
Rating
1.1 to 2.7
1.65 to 3.6
0 to 3.6
0 to 3.6
±
3
Unit
V
V
(Note 3)
(Note 5)
(Note 6)
(Note 7)
°C
(Note 8)
ns/V
mA
V
0 to V
CCB
(Note 4)
±
2
±
0.5
−
40 to 85
I
OUTB
T
opr
dt/dv
0 to 10
Note 1: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
Note 2: Don’t use in V
CCA
>
V
CCB
Note 3: Output in OFF state
Note 4: High or low state
Note 5: V
CCB
=
3.0 to 3.6 V
Note 6: V
CCB
=
2.3 to 2.7 V
Note 7: V
CCB
=
1.65 to 1.95 V
Note 8: V
IN
=
0.8 to 2.0 V, V
CCA
=
2.5 V, V
CCB
=
3.0 V
3
2014-03-01
TC7WPN3125FK/FC
AC Characteristics
(Ta
= −40
to 85°C, Input: t
r
=
t
f
=
2.0 ns)
V
CCA
=
2.5
±
0.2 V, V
CCB
=
3.3
±
0.3 V
Characteristics
Propagation delay time
(An
→
Bn)
3-state output enable time
( OE
→
Bn)
3-state output disable time
(
OE
→
Bn)
Output to output skew
Symbol
t
pLH
t
pHL
t
pZL
t
pZH
t
pLZ
t
pHZ
t
osLH
t
osHL
Test Condition
Figure 1, Figure 2
Min
1.0
Max
13.7
Unit
Figure 1, Figure 3
1.0
16.6
ns
Figure 1, Figure 3
1.0
7.2
(Note)
⎯
0.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
−
t
pLHn
|, t
osHL
=
|t
pHLm
−
t
pHLn
|)
V
CCA
=
1.8
±
0.15 V, V
CCB
=
3.3
±
0.3 V
Characteristics
Propagation delay time
(An
→
Bn)
3-state output enable time
( OE
→
Bn)
3-state output disable time
( OE
→
Bn)
Output to output skew
Symbol
t
pLH
t
pHL
t
pZL
t
pZH
t
pLZ
t
pHZ
t
osLH
t
osHL
Test Condition
Figure 1, Figure 2
Min
1.0
Max
14.8
Unit
Figure 1, Figure 3
1.0
18.9
ns
Figure 1, Figure 3
1.0
8.7
(Note)
⎯
0.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
−
t
pLHn
|, t
osHL
=
|t
pHLm
−
t
pHLn
|)
V
CCA
=
1.5
±
0.1 V, V
CCB
=
3.3
±
0.3 V
Characteristics
Propagation delay time
(An
→
Bn)
3-state output enable time
(
OE
→
Bn)
3-state output disable time
( OE
→
Bn)
Output to output skew
Symbol
t
pLH
t
pHL
t
pZL
t
pZH
t
pLZ
t
pHZ
t
osLH
t
osHL
Test Condition
Figure 1, Figure 2
Min
1.0
Max
16.0
Unit
Figure 1, Figure 3
1.0
22.8
ns
Figure 1, Figure 3
1.0
10.2
(Note)
⎯
1.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
−
t
pLHn
|, t
osHL
=
|t
pHLm
−
t
pHLn
|)
5
2014-03-01
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