LIF-MD6000-6JMG80I datasheet, PDF

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LIF-MD6000-6JMG80I: DescriptionLATTCE CROSSLNK - NTERFACE MP D-; CategoryProgrammable logic devices Programmable logic; File Size1MB，58 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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LIF-MD6000-6JMG80I Overview

LATTCE CROSSLNK - NTERFACE MP D-

LIF-MD6000-6JMG80I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	VFBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PBGA-B80
length	6.5 mm
Configurable number of logic blocks	1500
Number of terminals	80
organize	1500 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Maximum seat height	1 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6.5 mm
Base Number Matches	1

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CrossLink Family

Data Sheet

FPGA-DS-02007 Version 1.5

July 2018

CrossLink Family

Data Sheet

Contents

Acronyms in This Document ................................................................................................................................................. 5

1. General Description ...................................................................................................................................................... 6

1.1.

Features ............................................................................................................................................................... 6

2. Product Feature Summary ............................................................................................................................................ 7

3. Architecture Overview .................................................................................................................................................. 8

3.1.

MIPI D-PHY Blocks ............................................................................................................................................... 9

3.2.

Programmable I/O Banks .................................................................................................................................. 14

3.3.

sysI/O Buffers .................................................................................................................................................... 15

3.3.1. Programmable PULLMODE Settings .............................................................................................................15

3.3.2. Output Drive Strength ...................................................................................................................................15

3.3.3. On-Chip Termination ....................................................................................................................................15

3.4.

Programmable FPGA Fabric .............................................................................................................................. 16

3.4.1. PFU Blocks .....................................................................................................................................................16

3.4.2. Slice ...............................................................................................................................................................17

3.5.

Clocking Structure ............................................................................................................................................. 19

3.5.1. sysCLK PLL .....................................................................................................................................................19

3.5.2. Primary Clocks ...............................................................................................................................................20

3.5.3. Edge Clocks ...................................................................................................................................................20

3.5.4. Dynamic Clock Enables .................................................................................................................................21

3.5.5. Internal Oscillator (OSCI) ...............................................................................................................................21

3.6.

Embedded Block RAM Overview ....................................................................................................................... 22

3.7.

Power Management Unit .................................................................................................................................. 23

3.7.1. PMU State Machine ......................................................................................................................................23

3.8.

User I

C IP .......................................................................................................................................................... 24

3.9.

Programming and Configuration ....................................................................................................................... 25

4. DC and Switching Characteristics................................................................................................................................ 26

4.1.

Absolute Maximum Ratings .............................................................................................................................. 26

4.2.

Recommended Operating Conditions ............................................................................................................... 26

4.3.

Power Supply Ramp Rates................................................................................................................................. 27

4.4.

Power-On-Reset Voltage Levels ........................................................................................................................ 27

4.5.

ESD Performance ............................................................................................................................................... 27

4.6.

DC Electrical Characteristics .............................................................................................................................. 28

4.7.

CrossLink Supply Current................................................................................................................................... 29

4.8.

Power Management Unit (PMU) Timing ........................................................................................................... 30

4.9.

sysI/O Recommended Operating Conditions .................................................................................................... 30

4.10. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31

4.11. sysI/O Differential Electrical Characteristics ..................................................................................................... 31

4.11.1.

LVDS/subLVDS/SLVS200 ...........................................................................................................................31

4.11.2.

Hardened MIPI D-PHY I/Os .......................................................................................................................32

4.12. CrossLink Maximum General Purpose I/O Buffer Speed ................................................................................... 33

4.13. CrossLink External Switching Characteristics .................................................................................................... 34

4.14. sysCLOCK PLL Timing ......................................................................................................................................... 40

4.15. Hardened MIPI D-PHY Performance.................................................................................................................. 41

4.16. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 41

4.17. User I

C .............................................................................................................................................................. 41

4.18. CrossLink sysCONFIG Port Timing Specifications .............................................................................................. 42

4.19. SRAM Configuration Time from NVCM ............................................................................................................. 42

4.20. Switching Test Conditions ................................................................................................................................. 43

5. Pinout Information ..................................................................................................................................................... 44

5.1.

WLCSP36 Pinout ................................................................................................................................................ 44

5.2.

ucfBGA64 Pinout ............................................................................................................................................... 45

5.3.

ctfBGA80/cktBGA80 Pinout ............................................................................................................................... 47

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02007-1.5

CrossLink Family

Data Sheet

5.4.

csfBGA81 Pinout ................................................................................................................................................ 49

5.5.

Dual Function Pin Descriptions ......................................................................................................................... 51

5.6.

Dedicated Function Pin Descriptions ................................................................................................................ 51

5.7.

Pin Information Summary ................................................................................................................................. 52

6. CrossLink Part Number Description ............................................................................................................................ 53

6.1.

Ordering Part Numbers ..................................................................................................................................... 53

References .......................................................................................................................................................................... 54

Technical Support ............................................................................................................................................................... 54

Revision History .................................................................................................................................................................. 55

Figures

Figure 3.1. CrossLink Device Block Diagram ......................................................................................................................... 8

Figure 3.2. CrossLink sysI/O Banking .................................................................................................................................... 9

Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 10

Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 11

Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ...................................................................................... 12

Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module.................................................................................... 13

Figure 3.7. CrossLink Device Simplified Block Diagram (Top Level) .................................................................................... 16

Figure 3.8. CrossLink PFU Diagram ..................................................................................................................................... 16

Figure 3.9. Slice Diagram .................................................................................................................................................... 17

Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 18

Figure 3.11. CrossLink PLL Block Diagram ........................................................................................................................... 19

Figure 3.12. CrossLink Clocking Structure ........................................................................................................................... 20

Figure 3.13. CrossLink Edge Clock Sources per Bank .......................................................................................................... 21

Figure 3.14. CrossLink OSCI Component Symbol ................................................................................................................ 21

Figure 3.15. CrossLink MIPI D-PHY Block ............................................................................................................................ 23

Figure 3.16. CrossLink PMU State Machine ........................................................................................................................ 24

Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 38

Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 38

Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 38

Figure 4.4. Transmit TX.CLK.Aligned Waveforms ............................................................................................................... 39

Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 39

Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 43

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02007-1.5

CrossLink Family

Data Sheet

Tables

Table 2.1. CrossLink Feature Summary .................................................................................................................................7

Table 3.1. CrossLink Output Support per Bank Basis ..........................................................................................................14

Table 3.2. CrossLink Input Support per Bank Basis .............................................................................................................15

Table 3.3. Drive Strength Values .........................................................................................................................................15

Table 3.4. Slice Signal Descriptions .....................................................................................................................................18

Table 3.5. CrossLink PLL Port Definition .............................................................................................................................19

Table 3.6. OSCI Component Port Definition .......................................................................................................................21

Table 3.7. OSCI Component Attribute Definition ...............................................................................................................21

Table 3.8. sysMEM Block Configurations ............................................................................................................................22

Table 3.9. CrossLink sysCONFIG Pins ..................................................................................................................................25

Table 4.1. Absolute Maximum Ratings

1, 2, 3

........................................................................................................................26

Table 4.2. Recommended Operating Conditions

1, 2

...........................................................................................................26

Table 4.3. Power Supply Ramp Rates* ...............................................................................................................................27

Table 4.4. Power-On-Reset Voltage Levels 1, 3, 4 ..............................................................................................................27

Table 4.5. DC Electrical Characteristics ...............................................................................................................................28

Table 4.6. CrossLink Supply Current ...................................................................................................................................29

Table 4.7. PMU Timing* ......................................................................................................................................................30

Table 4.8. sysI/O Recommended Operating Conditions

....................................................................................................30

Table 4.9. sysI/O Single-Ended DC Electrical Characteristics ..............................................................................................31

Table 4.10. LVDS/subLVDS1/SLVS200

1, 2

............................................................................................................................31

Table 4.11. MIPI D-PHY .......................................................................................................................................................32

Table 4.12. CrossLink Maximum I/O Buffer Speed .............................................................................................................33

Table 4.13. CrossLink External Switching Characteristics

4, 5

..............................................................................................34

Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................40

Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)* ..........41

Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............41

Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................41

Table 4.18. Internal Oscillators ...........................................................................................................................................41

Table 4.19. User I

..........................................................................................................................................................41

Table 4.20. CrossLink sysCONFIG Port Timing Specifications .............................................................................................42

Table 4.21. SRAM Configuration Time from NVCM ............................................................................................................42

Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces* ..................................................................43

Table 5.1. WLCSP36 Pinout .................................................................................................................................................44

Table 5.2. ucfBGA64 Pinout ................................................................................................................................................45

Table 5.3. ctfBGA80/cktBGA80 Pinout ...............................................................................................................................47

Table 5.4. csfBGA81 Pinout .................................................................................................................................................49

Table 5.5. Dual Function Pin Descriptions ..........................................................................................................................51

Table 5.6. Dedicated Function Pin Descriptions .................................................................................................................51

Table 5.7. Pin Information Summary ..................................................................................................................................52

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02007-1.5

LIF-MD6000-6JMG80I Related Products

	LIF-MD6000-6JMG80I	LIF-MD6000-6UWG36ITR	LIF-MD6000-6KMG80I	LIF-MD6000-6UMG64ITR	LIF-MD6000-6UMG64ITR1K	LIF-MD6000-6UMG64I	LIF-MD6000-6MG81I	LIF-MD6000-6UWG36ITR50	LIF-MD6000-6UWG36ITR1K
Description	LATTCE CROSSLNK - NTERFACE MP D-	FPGA - Field Programmable Gate Array Crosslink Interface MIPI D-Phy Bridge	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-	LATTCE CROSSLNK - NTERFACE MP D-

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