LTC1408
6 Channel, 14-Bit, 600ksps
Simultaneous Sampling ADC
with Shutdown
DESCRIPTIO
The LTC
®
1408 is a 14-bit, 600ksps ADC with six simulta-
neously sampled differential inputs. The device draws
only 5mA from a single 3V supply, and comes in a tiny 32
pin (5mm
×
5mm) QFN package. A SLEEP shutdown
feature lowers power consumption to 6µW. The combina-
tion of low power and tiny package makes the LTC1408
suitable for portable applications.
The LTC1408 contains six separate differential inputs that
are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 100ksps per channel.
The 90dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or
±1.25V
bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
FEATURES
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600ksps ADC with 6 Simultaneously Sampled
Differential Inputs
100ksps Throughput per Channel
76dB SINAD
Low Power Dissipation: 15mW
3V Single Supply Operation
2.5V Internal Bandgap Reference, Can be Overdriven
with External Reference
3-Wire Serial Interface
Internal Conversion Triggered by CONV
SLEEP (6µW) Shutdown Mode
NAP (3.3mW) Shutdown Mode
0V to 2.5V Unipolar, or
±1.25V
Bipolar Differential
Input Range
90dB Common Mode Rejection
Tiny 32-Pin (5mm
×
5mm) QFN Package
APPLICATIO S
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Multiphase Power Measurement
Multiphase Motor Control
Data Acquisition Systems
Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including 6084440, 6522187.
BLOCK DIAGRA
CH5
–
CH5
+
CH4
–
CH4
+
21
20
19
18
17
CH3
–
CH3
+
CH2
–
CH2
+
CH1
–
CH1
+
CH0
–
CH0
+
10µF
V
CC
16
15
14
12
13
11
10
9
8
7
6
5
4
24
–
–
S AND H
–
–
–
–
S AND H
S AND H
S AND H
S AND H
S AND H
600ksps
14-BIT ADC
MUX
TIMING
LOGIC
30
32
V
REF
10µF
23
29
BIP
26
27
28
1408 TA01
2.5V
REFERENCE
GND
33
22
U
W
U
3V
V
DD
25
14-BIT LATCH 0
14-BIT LATCH 1
14-BIT LATCH 2
14-BIT LATCH 3
14-BIT LATCH 4
14-BIT LATCH 5
OV
DD
3V
SD0
0.1µF
2
OGND
+
+
+
+
+
+
THREE-
STATE
SERIAL
OUTPUT
PORT
3
1
CONV
SCK
DGND
31
SEL2 SEL1 SEL0
1408fa
1
LTC1408
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
16 15 14 13 12 11 10 9
CH4
+
17
CH4
–
18
GND 19
CH5
+
20
CH5
–
Supply Voltage (V
DD
, V
CC
, OV
DD
) .............................. 4V
Analog Input Voltage
(Note 3) ................................... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1408C ............................................... 0°C to 70°C
LTC1408I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
ORDER PART
NUMBER
8
7
6
CH1
–
CH1
+
GND
CH0
–
CH0
+
OV
DD
OGND
SDO
CH3
–
CH3
+
CH2
–
CH2
+
GND
GND
GND
GND
21
33
5
4
3
2
1
LTC1408CUH
LTC1408IUH
QFN PART MARKING
1408
GND 22
V
REF
23
V
CC
24
25 26 27 28 29 30 31 32
V
DD
BIP
SEL2
SEL1
SEL0
CONV
QFN PACKAGE
32-PIN (5mm
×
5mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 34°C/ W
EXPOSED PIN IS GND (PAD 33)
MUST BE SOLDERED TO PCB
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Offset Match from CH0 to CH5
Range Error
Range Match from CH0 to CH5
Range Tempco
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V, V
DD
= V
CC
= 3V.
CONDITIONS
●
DGND
SCK
MIN
14
–3
–4.5
–3
–12
–5
●
●
●
TYP
±0.5
±1
±0.5
±2
±1
±15
±1
MAX
3
4.5
3
12
5
UNITS
Bits
LSB
mV
mV
mV
mV
ppm/°C
ppm/°C
(Note 5)
(Note 4)
(Note 4)
Internal Reference (Note 4)
External Reference
A ALOG I PUT
SYMBOL PARAMETER
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
t
SK
CMRR
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V, V
DD
= V
CC
= 3V.
CONDITIONS
2.7V
≤
V
DD
≤
3.3V
(Note 8)
●
MIN
TYP
0 to 2.5
0 to V
DD
MAX
UNITS
V
V
Analog Differential Input Range (Notes 3, 8, 9)
Analog Common Mode + Differential
Input Range
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Channel to Channel Aperture Skew
Analog Input Common Mode Rejection Ratio
1
13
39
1
0.3
200
(Note 6)
●
f
IN
= 100kHz, V
IN
= 0V to 3V
f
IN
= 10MHz, V
IN
= 0V to 3V
–83
–67
1408fa
2
U
µA
pF
ns
ns
ps
ps
dB
dB
W
U
U
W W
W
U
U
U
LTC1408
DY A IC ACCURACY
SYMBOL
SINAD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V, V
DD
= V
CC
= 3V.
CONDITIONS
100kHz Input Signal
300kHz Input Signal
100kHz Input Signal, External V
REF
= 3.3V, V
DD
≥
3.3V
300kHz Input Signal, External V
REF
= 3.3V, V
DD
≥
3.3V
100kHz First 5 Harmonics
300kHz First 5 Harmonics
100kHz Input Signal
300kHz Input Signal
0.625V
P-P
, 833kHz into CH0+, 0.625V
P-P
, 841kHz into CH0–.
Bipolar Mode. Also Applicable to Other Channels
V
REF
= 2.5V (Note 17)
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(–3dBFS) (Note 15)
S/(N + D)
≥
68dB, Bipolar Differential Input
●
THD
SFDR
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
CONDITIONS
I
OUT
= 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3V
V
OUT
= V
DD
= 3V
CONDITIONS
V
DD
= 3.3V
V
DD
= 2.7V
V
IN
= 0V to V
DD
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
●
●
●
U
U
U
W U
U
MIN
73
TYP
76
76
79
79
–90
–86
90
86
–80
0.7
50
5
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
LSB
RMS
MHz
MHz
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
Full Power Bandwidth
Full Linear Bandwidth
●
–80
U
T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
TYP
2.5
15
600
0.2
2
MAX
UNITS
V
ppm/°C
µV/V
Ω
ms
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
TYP
MAX
0.6
±10
UNITS
V
V
µA
pF
V
V
V
µA
pF
mA
mA
2.4
5
V
DD
= 3V, I
OUT
= – 200µA
V
DD
= 2.7V, I
OUT
= 160µA
V
DD
= 2.7V, I
OUT
= 1.6mA
V
OUT
= 0V and V
DD
●
●
●
2.5
2.9
0.05
0.4
±10
1
20
15
1408fa
3
LTC1408
POWER REQUIRE E TS
SYMBOL
V
DD
, V
CC
I
DD
+ I
CC
PARAMETER
Supply Voltage
Supply Current
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
Active Mode, f
SAMPLE
= 600ksps
Nap Mode
Sleep Mode
Active Mode with SCK, f
SAMPLE
= 600ksps
●
●
PD
Power Dissipation
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V.
SYMBOL
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
(Note 16)
(Notes 6, 17)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
CONDITIONS
●
●
●
TI I G CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2:
All voltage values are with respect to ground GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and range specifications apply for a single-ended CH0
+
–
CH5
+
input with CH0
–
– CH5
–
grounded and using the internal 2.5V
reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between CHx
+
and CHx
–
, x = 0–5.
4
U W
MIN
2.7
TYP
5
1.1
2.0
15
MAX
3.6
7
1.9
15
UNITS
V
mA
mA
µA
mW
UW
MIN
100
TYP
MAX
UNITS
kHz
667
100
96
2
3
0
4
4
1.2
45
8
6
2
2
10000
10000
ns
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 9:
The absolute voltage at CHx
+
and CHx
–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17:
The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
1408fa
LTC1408
TYPICAL PERFOR A CE CHARACTERISTICS
SINAD, ENOBs vs Frequency
77
74
71
12.5
12
11.5
11
10.5
10
UNIPOLAR SINGLE
ENDED
BIPOLAR
DIFFERENTIAL
0.1
1
10
FREQUENCY (MHz)
100
1408 G01
SINAD (dB)
68
65
62
59
56
53
THD (dB)
3rd
THD (dB)
SFDR vs Input Frequency
104
98
92
86
BIPOLAR DIFFERENTIAL
76
75
74
73
72
OUTPUT MAGNITUDE (dB)
SFDR (dB)
SNR (dB)
80
74
68
62
56
50
44
0.1
1
10
FREQUENCY (MHz)
100
1408 G04
UNIPOLAR SINGLE ENDED
98kHz Bipolar Sine Wave 4096
Point FFT Plot, 100 ksps
0
–10
–20
OUTPUT MAGNITUDE (dB)
OUTPUT MAGNITUDE (dB)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30
FREQUENCY(kHz)
40
50
1408 G07
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30
FREQUENCY(kHz)
40
50
1408 G08
OUTPUT MAGNITUDE (dB)
U W
V
DD
= 3V, T
A
= 25°C
THD, 2nd and 3rd
vs Input Frequency
–44
–50
BIPOLAR SINGLE ENDED
V
CM
= 1.5V
THD, 2nd and 3rd
vs Input Frequency
–44
–50
–56
–62
5 HARMONIC THD
2nd
UNIPOLAR SINGLE ENDED
–56
–62
–68
–74
–80
–86
–92
–98
–104
2nd
5 HARMONIC THD
3rd
ENOBS (bits)
–68
–74
–80
–86
–92
–98
–104
0.1
9.5
9
8.5
1
10
FREQUENCY (MHz)
100
1408 G02
0.1
1
10
FREQUENCY (MHz)
100
1408 G03
SNR vs Input Frequency
0
BIPOLAR
DIFFERENTIAL
98kHz Unipolar Sine Wave 4096
Point FFT Plot, 100 ksps
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
71
70
69
68
67
66
65
64
0.1
UNIPOLAR
SINGLE ENDED
1
10
FREQUENCY (MHz)
100
1408 G05
0
10
20
30
FREQUENCY(kHz)
40
50
1408 G06
591kHz Bipolar Differential Sine
Wave 4096 Point FFT Plot,
100 ksps
0
–10
–20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
101kHz Unipolar Single Ended
Sine Wave 4096 Point FFT Plot,
625 ksps
0
62.5
125
188
FREQUENCY(kHz)
250
313
1408 G09
1408fa
5
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