UT7R995C-XPX datasheet, PDF - EEWORLD Datasheet

Standard Products

UT7R995 & UT7R995C RadClock

TM

RadHard 2.5V/3.3V 200MHz High-Speed

Multi-phase PLL Clock Buffer

Datasheet

February, 2007

FEATURES:

+3.3V Core Power Supply

+2.5V or +3.3V Clock Output Power Supply

- Independent Clock Output Bank Power Supplies

Output frequency range: 6 MHz to 200 MHz

Bank pair output-output skew < 100 ps

Cycle-cycle jitter < 50 ps

50% ± 2% maximum output duty cycle at 100MHz

Eight LVTTL outputs with selectable drive strength

Selectable positive- or negative-edge synchronization

Selectable phase-locked loop (PLL) frequency range and

lock indicator

Phase adjustments in 625 to 1300 ps steps up to ± 7.8 ns

(1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios

Compatible with Spread-Spectrum reference clocks

Power-down mode

Selectable reference input divider

Radiation performance

- Total-dose tolerance: 100 krad (Si)

- SEL Immune to a LET of 109 MeV-cm

2

/mg

- SEU Immune to a LET of 109 MeV-cm

2

/mg

Military temperature range: -55

o

C to +125

o

C

Extended industrial temp: -40

o

C to +125

o

C

Packaging options:

- 48-Lead Ceramic Flatpack

Standard Microcircuit Drawing: 5962-05214

- QML-Q and QML-V compliant part

The devices also feature split output bank power supplies that

enable banks 1 & 2, bank 3, and bank 4 to operate at a different

power supply levels. The ternary PE/HD pin controls the syn-

chronization of output signals to either the rising or the falling

edge of the reference clock and selects the drive strength of the

output buffers. The UT7R995 and UT7R995C both interface

to a digital clock while the UT7R995C will also interface to a

quartz crystal.

INTRODUCTION:

The UT7R995/UT7R995C is a low-voltage, low-power, eight-

output, 6-to-200 MHz clock driver. It features output phase

programmability which is necessary to optimize the timing of

high-performance microprocessor and communication sys-

tems.

The user programs both the frequency and the phase of the out-

put banks through nF[1:0] and DS[1:0] pins. The adjustable

phase feature allows the user to skew the outputs to lead or lag

the reference clock. Connect any one of the outputs to the

feedback input to achieve different reference frequency multi-

plication and division ratios.

4F0

4F1

sOE

PD/DIV

PE/HD

V

DD

V

DD

Q3

3Q1

3Q0

V

SS

V

SS

V

DD

FB

V

DD

V

SS

V

SS

2Q1

2Q0

V

DD

Q1

LOCK

V

SS

DS0

DS1

1F0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

UT7R995

&

UT7R995C

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

3F1

3F0

FS

V

SS

V

SS

V

DD

Q4

4Q1

4Q0

V

SS

V

SS

V

DD

XTAL1

NC/XTAL2

V

DD

V

SS

V

SS

1Q1

1Q0

V

DD

Q1

V

SS

TEST

2F1

2F0

1F1

Figure 1. 48-Lead Ceramic Flatpack Pin Description

1

TEST

PE/HD

FS

V

DDQ1

PD/DIV

XTAL1

3

/R

3

LOCK

NC/XTAL2

PLL

/N

3

DS[1:0]

3

1F[1:0]

3

FB

1Q0

Phase

Select

1Q1

3

2F[1:0]

3

Phase

Select

2Q0

2Q1

3

3F[1:0]

3

Phase

Select

and /K

3Q0

3Q1

V

DDQ3

3

4F[1:0]

3

Phase

Select

and /M

4Q0

4Q1

V

DDQ4

Figure 2. UT7R995 & UT7R995C Block Diagram

sOE

2

1.0 DEVICE CONFIGURATION:

The outputs of the UT7R995/C can be configured to run at fre-

quencies ranging from 6 MHz to 200 MHz. Each output bank

has the ability to run at separate frequencies and with various

phase skews. Furthermore, numerous clock division and multi-

plication options exist.

The following discussion and list of tables will summarize the

available configuration options for the UT7R995/C. Tables 1

through 12, are relevant to the following configuration discus-

sions.

Table 1. Feedback Divider Settings (N-factor)

Table 2. Reference Divider Settings (R-Factor)

Table 3. Output Divider Settings - Bank 3 (K-factor)

Table 4. Output Divider Settings - Bank 4 (M-Factor)

Table 5. Frequency Divider Summary

Table 6. Calculating Output Frequency Settings

Table 7. Frequency Range Select

Table 8. Multiplication Factor (MF) Calculation

Table 9. Signal Propagation Delays in Various Media

Table 10: Output Skew Settings

Table 11. PE/HD Settings

Table 12. Power Supply Constraints

1.1 Divider Configuration Settings:

The feedback input divider is controlled by the 3-level DS[1:0]

pins as indicated in Table 1 and the reference input divider is

controlled by the 3-level PD/DIV pin as indicated in Table 2.

Although the Reference divider will continue to operate when

the UT7R995/C is in the standard TEST mode of operation, the

Feedback Divider will not be available.

Table 1: Feedback Divider Settings (N-factor)

DS[1:0]

LL

LM

LH

ML

MM

MH

HL

HM

HH

Table 2: Reference Divider Settings (R-factor)

PD/DIV

LOW

1

MID

HIGH

Operating Mode

Powered Down

Normal Operation

Reference Input

Divider -

(R)

Not Applicable

2

1

Notes:

1. When PD/DIV = LOW, the device enters power-down mode.

In addition to the reference and feedback dividers, the

UT7R995/C includes output dividers on Bank 3 and Bank 4,

which are controlled by 3F[1:0] and 4F[1:0] as indicated in Ta-

bles 3 and 4, respectively.

Table 3: Output Divider Settings - Bank 3 (K-factor)

3F(1:0)

LL

HH

Other

1

Bank 3 Output Divider -

(K)

2

4

1

Notes:

1. These states are used to program the phase of the respective banks. Please see

Equation 1 along with Tables 8 and 10.

Table 4: Output Divider Settings - Bank 4 (M-factor)

4F[1:0]

LL

Other

1

Bank 4 Output Divider

(M)

2

1

Feedback Input

Divider -

(N)

2

3

4

5

1

6

8

10

12

Permitted Output

Divider (K or M)

Connected to FB

1 or 2

1

1, 2, or 4

1 or 2

1, 2, or 4

1 or 2

Notes:

1. These states are used to program the phase of the respective banks. Please see

Equation 1 along with Tables 8 and 10.

Each of the four divider options and their respective settings are

summarized in Table 5. By applying the divider options in Ta-

ble 5 to the calculations shown in Table 6, the user determines

the proper clock frequency for every output bank.

Table 5: Frequency Divider Summary

Division

Factors

N

Available Divider Settings

1, 2, 3, 4, 5, 6, 8, 10, 12

1, 2

1, 2, 4

1, 2

1

R

1

K

M

3

Table 6: Calculating Output Frequency Settings

Configuration

Clock Output

Connected to FB

1Qn or 2Qn

3Qn

4Qn

Output Frequency

1Q[1:0]

1

and

2Q[1:0]

1

(N/R) * f

XTAL

(N/R) * K * f

XTAL

(N/R) * M * f

XTAL

(N/R) * (1/K) * f

XTAL

(N/R) * f

XTAL

(N/R) * (M/K) * f

XTAL

(N/R) * (1/M) * f

XTAL

(N/R) * (K/M) * f

XTAL

(N/R) * f

XTAL

3Q[1:0]

4Q[1:0]

Notes:

1. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the nominal VCO operating frequency (f

NOM

)

at a given reference frequency (f

XTAL

) and the divider and feedback configuration. The user must select a configuration and a reference frequency that will generate

a VCO frequency that is within the range specified by FS pin. Please see Table 7.

1.2 Frequency Range and Skew Selection:

The PLL in the UT7R995/C operates within three nominal fre-

quency ranges. Depending upon the desired PLL operating fre-

quency, the user must define the state of the ternary FS control

pin. Table 7 defines the required FS selections based upon the

nominal PLL operating frequency ranges. Because the clock

outputs on Bank 1 and Bank 2 do not include a divider option,

they will always reflect the current frequency of the PLL. Ref-

erence the first column of equations in Table 6 to calculate the

value of f

NOM

for any given feedback clock.

Table 7: Frequency Range Select

FS

L

M

H

After calculating the time unit (t

U

) based on the nominal PLL

frequency (f

NOM

) and multiplication factor (MF), the circuit

designer plans routing requirements of each clock output and its

respective destination receiver. With an understanding of signal

propagation delays through a conductive medium (see Table 9),

the designer specifies trace lengths which ensure a signal prop-

agation delay that is equal to one of the t

U

multiples show in Ta-

ble 10. For each output bank, the t

U

skew factors are selected

with the tri-level, bank-specific, nF[1:0] pins.

Table 8: MF Calculation

FS

L

M

H

MF

32

16

8

Nominal PLL Frequency Range

(f

NOM

)

24 to 50 MHz

48 to 100MHz

96 to 200 MHz

f

NOM

examples that result

in a t

U

of 1.0ns

31.25 MHz

62.5 MHz

125 MHz

Selectable output skew is in discrete increments of time unit

(t

U

). The value of t

U

is determined by the FS setting and the

PLL’s operating frequency (f

NOM

). Use the following equation

to calculate the time unit (t

U

):

Equation 1.

t

=

1

(f

NOM

* MF)

Table 9: Signal Propagation Delays in Various Media

Medium

Air (Radio Waves)

Coax. Cable (75% Velocity)

Coax. Cable (66% Velocity)

FR4 PCB, Outer Trace

FR4 PCB, Inner Trace

Alumina PCB, Inner Trace

Propagation

Dielectric

Delay (ps/inch) Constant

85

113

129

140 - 180

180

240 - 270

1.0

1.8

2.3

2.8 - 4.5

4.5

8 - 10

u

The f

NOM

term, which is calculated with the help of Table 6,

must be compatible with the nominal frequency range selected

by the FS signal as defined in Table 7. The multiplication factor

(MF), also determined by FS, is shown in Table 8. The

UT7R995/C output skew steps have a typical accuracy of +/-

15% of the calculated time unit (t

U

).

4

Table 10: Output Skew Settings

4

nF[1:0]

LL

1, 2

LM

LH

ML

MM

MH

HL

HM

HH

2

Skew

1Q[1:0], 2Q[1:0]

-4t

U

-3t

U

-2t

U

-1t

U

Zero Skew

+1t

U

+2t

U

+3t

U

+4t

U

Skew

3Q[1:0]

Divide by 2

-6t

U

-4t

U

-2t

U

Zero Skew

+2t

U

+4t

U

+6t

U

Divide by 4

Skew

4Q[1:0]

Divide by 2

-6t

U

-4t

U

-2t

U

Zero Skew

+2t

U

+4t

U

+6t

U

Inverted

3

A graphical summary of Table 10 is shown in Figure 3. The

drawing assumes that the FB input is driven by a clock output

programmed with zero skew. Depending upon the state of the

nF[1:0] pins the respective clocks will be skewed, divided, or

inverted relative to the fedback output as shown in Figure 3.

1.3 Output Drive, Synchronization, and Power Supplies:

The UT7R995/C employs flexible output buffers providing the

user with selectable drive strengths, independent power sup-

plies, and synchronization to either edge of the reference input.

Using the 3-level PE/HD pin, the user selects the reference edge

synchronization and the output drive strength for all clock out-

puts. The options for edge synchronization and output drive

strength selected by the PE/HD pin are listed in Table 11.

Table 11: PE/HD Settings

PE/HD

Synchronization

Output Drive

Strength

1

L

M

H

Negative

Positive

Low Drive

High Drive

Low Drive

Notes:

1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.

2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion-

options function as defined in Table 9.

3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-

puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when

PE/HD = LOW.

4. Skew accuracy is within +/- 15% of n*t

U

where "n" is the selected number

of skew steps. Supplied as a design limit, but not tested or guaranteed.

Notes:

1. Please refer to "DC Parameters" section for I

OH

/I

OL

specifications.

XTAL1 Input

FB Input

1F[1:0]

(N/A)

LL

LM

LH

ML

MM

MH

HL

HM

HH

(N/A)

2F[1:0]

(N/A)

LL

LM

LH

ML

MM

MH

HL

HM

HH

(N/A)

3F[1:0]

LM

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

(N/A)

4F[1:0]

LM

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL

HH

-6t

U

-4t

U

-3t

U

-2t

U

-1t

U

0t

U

+1t

U

+2t

U

+3t

U

+4t

U

+6t

U

DIVIDED

INVERTED

Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output

5

t

0

- 5t

U

t

0

- 4t

U

t

0

- 3t

U

t

0

- 2t

U

t

0

- 1t

U

t

0

t

0

+ 1t

U

t

0

+ 2t

U

t

0

+ 3t

U

t

0

+ 4t

U

t

0

+ 5t

U

t

0

+ 6t

U

t

0

- 6t

U

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