U62H256AS2K35LL datasheet, PDF

U62H256A

Automotive Fast 32K x 8 SRAM

Features

!

32768 x 8 bit static CMOS RAM

!

35 and 55 ns Access Time

!

Common data inputs and

!

Description

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

!

The U62H256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

data outputs

- Read

- Standby

Three-state outputs

- Write

- Data Retention

Typ. operating supply current

The memory array is based on a

35 ns: 45 mA

6-transistor cell.

55 ns: 30 mA

Standby current < 50 µA at 125 °C The circuit is activated by the fal-

ling edge of E. The address and

TTL/CMOS-compatible

control inputs open simultaneously.

Power supply voltage 5 V

According to the information of W

Operating temperature range

-40 °C to 85 °C

and G, the data inputs, or outputs,

-40 °C to 125 °C

are active. In a Read cycle, the

data outputs are activated by the

QS 9000 Quality Standard

falling edge of G, afterwards the

ESD protection > 2000 V

(MIL STD 883C M3015.7)

data word will be available at the

outputs DQ0-DQ7. After the

Latch-up immunity >100 mA

address change, the data outputs

Package: SOP28 (300/330 mil)

Pin Configuration

Pin Description

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

VCC

W

A13

A8

A9

A11

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A14

DQ0 - DQ7

E

G

W

VCC

VSS

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

22

21

20

19

18

17

16

15

Top View

April 20, 2004

1

U62H256A

Block Diagram

A6

A7

A8

A9

A10

A11

A12

A13

A14

Row Address

Inputs

Row Decoder

Memory Cell

Array

512 Rows x

64 x 8 Columns

Common Data I/O

A0

A1

A2

A3

A4

A5

Column Address

Inputs

Column Decoder

DQ0

Sense Amplifier/

Write Control Logic

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Address

Change

Detector

Clock

Generator

V

CC

V

SS

E

W

G

Truth Table

Operating Mode

Standby/not selected

Internal Read

Read

Write

* H or L

E

H

L

W

*

H

L

G

*

H

L

*

DQ0 - DQ7

High-Z

Data Outputs Low-Z

Data Inputs High-Z

2

April 20, 2004

U62H256A

Characteristics

All voltages are referenced to V

SS

= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of

≤

5 ns, measured between 10 % and 90 % of V

I

, as well as

input levels of V

IL

= 0 V and V

IH

= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t

dis

-times and t

en

-times, in which cases transition is measured ±200 mV from steady-state voltage.

Absolute Maximum Ratings

a

Power Supply Voltage

Input Voltage

Output Voltage

Power Dissipation

Operating Temperature

Storage Temperature

Output Short-Circuit Current

at V

CC

= 5 V and V

O

= 0 V

c

a

Symbol

V

CC

V

I

V

O

P

D

Min.

-0.5

-

-40

-65

Max.

7

V

CC

+ 0.5

b

V

CC

+ 0.5

b

1

85

125

150

200

Unit

V

W

°C

mA

K-Type

A-Type

T

a

T

stg

| I

OS

|

b

c

Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only,

and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability

Maximum voltage is 7 V

Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Recommended

Operating Conditions

Power Supply Voltage

Input Low Voltage

d

Input High Voltage

d

Symbol

V

CC

V

IL

V

IH

Conditions

Min.

4.5

-0.3

2.2

Max.

5.5

0.8

V

CC

+ 0.3

Unit

V

-2 V at Pulse Width 10 ns

April 20, 2004

3

U62H256A

Electrical Characteristics

Supply Current - Operating Mode

Symbol

I

CC(OP)

V

CC

V

IL

V

IH

t

cW

t

cW

V

CC

V

E

K-Type

A-Type

V

CC

V

E

V

CC

I

OH

V

CC

I

OL

V

CC

V

IH

V

CC

V

IL

V

CC

V

OH

V

CC

V

OL

V

CC

V

OH

V

CC

V

OL

Conditions

=

5.5 V

0.8 V

2.2 V

35 ns

55 ns

Min.

Max.

Unit

90

70

mA

Supply Current - Standby Mode

(CMOS level)

I

CC(SB)

= 5.5 V

= V

CC

- 0.2 V

10

50

1

2.4

0.4

2

-2

-4

8

µA

mA

V

µA

mA

Supply Current - Standby Mode

(TTL level)

Output High Voltage

Output Low Voltage

Input High Leakage Current

Input Low Leakage Current

Output High Current

Output Low Current

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

I

CC(SB)1

V

OH

V

OL

I

IH

I

IL

I

OH

I

OL

= 5.5 V

= 2.2 V

= 4.5 V

= -4.0 mA

= 4.5 V

= 8.0 mA

= 5.5 V

= 0V

=

4.5 V

2.4 V

4.5 V

0.4 V

I

OHZ

I

OLZ

= 5.5 V

= 0V

2

-2

µA

4

April 20, 2004

U62H256A

Switching Characteristics

Read Cycle

Read Cycle Time

Address Access Time to Data Valid

Chip Enable Access Time to Data Valid

G LOW to Data Valid

E HIGH to Output in High-Z

G HIGH to Output in High-Z

E LOW to Output in Low-Z

G LOW to Output in Low-Z

Output Hold Time from Address Change

E LOW to Power-Up Time

E HIGH to Power-Down Time

Symbol

Alt.

t

RC

t

AA

t

ACE

t

OE

t

HZCE

t

HZOE

t

LZCE

t

LZOE

t

OH

t

PU

t

PD

IEC

t

cR

t

a(A)

t

a(E)

t

a(G)

t

dis(E)

t

dis(G)

t

en(E)

t

en(G)

t

v(A)

3

0

3

0

35

Min.

35

Max.

Min.

55

Unit

Max.

35

15

12

55

25

20

15

3

0

3

0

55

ns

Switching Characteristics

Write Cycle

Write Cycle Time

Write Pulse Width

Write Setup Time

Address Setup Time

Address Valid to End of Write

Chip Enable Setup Time

Pulse Width Chip Enable to End of Write

Data Setup Time

Data Hold Time

Address Hold from End of Write

W LOW to Output in High-Z

G HIGH to Output in High-Z

W HIGH to Output in Low-Z

G LOW to Output in Low-Z

Symbol

Alt.

t

WC

t

WP

t

WP

t

AS

t

AW

t

CW

t

CW

t

DS

t

DH

t

AH

t

HZWE

t

HZOE

t

LZWE

t

LZOE

IEC

t

cW

t

w(W)

t

su(W)

t

su(A)

t

su(A-WH)

Min.

35

Max.

Min.

55

Unit

Max.

35

20

0

25

15

0

15

12

0

55

35

0

40

25

0

20

15

0

ns

t

su(E)

t

w(E)

t

su(D)

t

h(D)

t

h(A)

t

dis(W)

t

dis(G)

t

en(W)

t

en(G)

April 20, 2004

5

U62H256AS2K35LL

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