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DM74AS573N

Description
IC LATCH OCTAL D-TYPE 3ST 20-DIP
Categorysemiconductor    logic   
File Size59KB,6 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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DM74AS573N Overview

IC LATCH OCTAL D-TYPE 3ST 20-DIP

DM74AS573N Parametric

Parameter NameAttribute value
logical typeD type transparent latch
circuit8:8
Output typeThree states
Voltage - Power4.5 V ~ 5.5 V
independent circuit1
Delay time - propagation3ns
Current - output high, low15mA,48mA
Operating temperature0°C ~ 70°C
Installation typeThrough hole
Package/casing20-DIP(0.300",7.62mm)
Supplier device packaging20-PDIP
DM74AS573 Octal D-Type Transparent Latch with 3-STATE Outputs
October 1986
Revised March 2000
DM74AS573
Octal D-Type Transparent Latch with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased HIGH-logic-level drive provide these registers
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The eight latches of the DM74AS573 are transparent D-
type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set UP.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pin-out is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all the
outputs are on the other side.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally equivalent with DM74S373
s
Improved AC performance over DM74S373 at approxi-
mately half the power
s
3-STATE buffer-type outputs drive bus lines directly
s
Bus structured pinout
Ordering Code:
Order Number
DM74AS573WM
DM74AS573N
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006313
www.fairchildsemi.com

DM74AS573N Related Products

DM74AS573N DM74AS573WM DM74AS573WMX
Description IC LATCH OCTAL D-TYPE 3ST 20-DIP IC LATCH OCTAL D-TYPE 3ST 20SOIC IC LATCH TRANSP OCT D 3ST 20SOIC
logical type D type transparent latch D type transparent latch D type transparent latch
circuit 8:8 8:8 8:8
Output type Three states Three states Three states
Voltage - Power 4.5 V ~ 5.5 V 4.5 V ~ 5.5 V 4.5 V ~ 5.5 V
independent circuit 1 1 1
Delay time - propagation 3ns 3ns 3ns
Current - output high, low 15mA,48mA 15mA,48mA 15mA,48mA
Operating temperature 0°C ~ 70°C 0°C ~ 70°C 0°C ~ 70°C
Installation type Through hole surface mount surface mount
Package/casing 20-DIP(0.300",7.62mm) 20-SOIC (0.295", 7.50mm wide) 20-SOIC (0.295", 7.50mm wide)
Supplier device packaging 20-PDIP 20-SOIC 20-SOIC

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