TSXPC603RMGSB/Q14L datasheet, PDF

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TSXPC603RMGSB/Q14L: DescriptionPowerPC 603e RISC Microprocessor Family PID7t-603e; File Size514KB，58 Pages; ManufacturerAtmel (Microchip)

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TSXPC603RMGSB/Q14L Overview

PowerPC 603e RISC Microprocessor Family PID7t-603e

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Features

•

Superscalar (3 Instructions per Clock Peak)

Dual 16 KB Caches

Selectable Bus Clock

32-bit Compatibility PowerPC Implementation

On-chip Debug Support

Nap, Doze and Sleep Power Saving Modes

Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255

Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255

•

7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)

Typically = 3.5W (266 MHz), Full Operating Conditions

Branch Folding

64-bit Data Bus (32-bit Data Bus Option)

4-Gbytes Direct Addressing Range

Pipelined Single/Double Precision Float Unit

IEEE 754 Compatible FPU

IEEE P 1149-1 Test Mode (JTAG/C0P)

INT

Max = 300 MHz

BUS

Max = 75 MHz

Compatible CMOS Input/TTL Output

PowerPC

603e

RISC

Microprocessor

Family

PID7t-603e

TSPC603R

Features Specific to Cerquad

•

5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)

•

Typically = 2.5W (200 MHz), Full Operating Conditions

1. Description

The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a

low-power implementation of the Reduced Instruction Set Computer (RISC) micropro-

cessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e

and 603P in a Cerquad package. The 603R implements 32-bit effective addresses,

integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603R is a low-power 2.5/3.3V design and provides four software controllable

power-saving modes. This device is a superscalar processor capable of issuing and

retiring as many as three instructions per clock. Instructions can be executed in any

order for increased performance, but, the 603R makes completion appear sequential.

It integrates five execution units and is able to execute five instructions in parallel.

The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physi-

cally addressed caches for instructions and data, as well as on-chip instructions, and

data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way

set-associative, data and instruction translation look aside buffers that provide support

for demand-paged virtual memory address translation and variable-sized block trans-

lation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The

interface protocol allows multiple masters to compete for system resources through a

central external arbiter. The device supports single-beat and burst data transfers for

memory accesses, and supports memory-mapped I/Os.

Rev. 5410B–HIREL–09/05

• a Load/Store Unit (LSU)

• a System Register Unit (SRU)

The ability to execute five instructions in parallel and the use of simple instructions with rapid

execution times yield high efficiency and throughput for 603R-based systems. Most integer

instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add

instruction can be issued every clock cycle.

The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically

addressed caches for instructions and data, as well as on-chip instruction and data Memory

Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative, Data and

Instruction Translation Lookaside Buffers (DTLB and ITLB) that provide support for

demand-paged virtual memory address translation and variable-sized block translation. The

TLBs and caches use a Least Recently Used (LRU) replacement algorithm. The 603R also sup-

ports block address translation through the use of two independent Instruction and Data Block

Address Translation (IBAT and DBAT) arrays of four entries each. Effective addresses are com-

pared simultaneously with all four entries in the BAT array during block translation. In

accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT

array, the BAT translation has priority.

The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface

protocol allows multiple masters to compete for system resources through a central external

arbiter. The 603R provides a three-state coherency protocol that supports the exclusive, modi-

fied, and invalid cache states. This protocol is a compatible subset of the MESI

(Modified/Exclusive/Shared/Invalid) four-state protocol and operates coherently in systems that

contain four-state caches. The 603R supports single-beat and burst data transfers for memory

accesses, and supports memory-mapped I/Os.

The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains

full interface compatibility with TTL devices.

5. Signal Description

Figure 5-1 on page 5, Table 10-5

and

Table 10-6 on page 20

describe the signals on the

TSPC603R and indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO,

comply with the subset P-1149.1 of the IEEE testability bus standard.

The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use

only and must be pulled up to V

for normal machine operations.

TSPC603R

5410B–HIREL–09/05

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