TN1504/TN1506/TN1510
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Features
► Low threshold - 2.0V max.
► High input impedance
► Low input capacitance - 50pF typical
► Fast switching speeds
► Low on resistance
► Free from secondary breakdown
► Low input and output leakage
► Complementary N- and P-channel devices
General Description
These low threshold enhancement-mode (normally-off)
transistors utilize a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This combi-
nation produces devices with the power handling capabilities
of bipolar transistors, and with the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input im-
pedance, low input capacitance, and fast switching speeds
are desired.
Applications
►
►
►
►
►
►
►
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-source voltage
Drain-to-source voltage
Operating and storage temperature
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Ordering Information
Device
TN1504
TN1506
TN1510
* Die in wafer form.
Order Number
Die*
TN1504NW
TN1506NW
TN1510NW
BV
DSS
/ BV
DGS
40V
60V
100V
R
DS(ON)
(max)
3.0Ω
3.0Ω
3.0Ω
V
GS(th)
(max)
2.0V
2.0V
2.0V
I
D(ON)
(min)
2.0A
2.0A
2.0A
1
TN1504/TN1506/TN1510
Electrical Characteristics
(@25 C unless otherwise specified)
O
Symbol
BV
DSS
V
GS(th)
∆V
GS(th)
I
GSS
I
DSS
Parameter
TN1504
Drain-to-source break-
down voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
TN1506
TN1510
Min
40
60
100
0.6
-
-
Typ
-
Max
-
Units
V
Conditions
V
GS
= 0V, I
D
= 1.0mA
V
GS
= V
DS
, I
D
= 0.5mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ±20V, V
DS
= 0V
V
GS
=0V, V
DS
= Max Rating
-
-3.8
0.1
2.0
-5.0
100
10
V
mV/
O
C
nA
Zero gate voltage drain current
-
-
500
μA
V
GS
= 0V, V
DS
= 0.8 Max Rating
T
A
= 125
O
C
V
GS
= 5V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 4.5V, I
D
= 250mA
V
GS
= 10V, I
D
= 500mA
V
GS
= 10V, I
D
= 0.5A
V
DS
= 25V, I
D
= 500mA
V
GS
= 0V, V
DS
= 25V f = 1 MHz
I
D(ON)
R
DS(ON)
∆R
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
ON-state drain current
Static drain-to-source ON-state
resistance
Change in R
DS(ON)
with temperature
Forward transconductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
Rise time
Turn-OFF delay time
Fall time
Diode forward voltage drop
Reverse recovery time
-
-
-
-
-
225
-
-
-
-
-
-
-
-
-
1.4
3.4
2.0
1.6
0.6
400
50
25
4.0
2.0
3.0
6.0
3.0
1.0
400
-
-
4.5
3.0
1.1
-
60
35
8.05
5.0
5.0
7.0
6.0
1.5
-
A
Ω
%/
O
C
mmho
pF
ns
V
DD
= 25V, I
D
= 1.0A
R
GEN
= 25Ω
V
ns
V
GS
= 0V, I
SD
= 0.5A
V
GS
= 0V, I
SD
= 0.5A
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
V
DD
10V
90%
INPUT
0V
10%
t
(ON)
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
L
OUTPUT
R
GEN
t
d(ON)
V
DD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
Doc.# DSFP-TN1504/TN1506/TN1510
062706
2
PCB Design
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