Integrated Circuit Systems, Inc.
ICS1893AG
Document Type:
Data Sheet
Document Stage: Preliminary
3.3 V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893AG is a re-packaged version of the ICS1893AF
in a 56-lead TSSOP 240 mil package. The ICS1893AG is a
fully integrated, Physical Layer device (PHY) that is
compliant with both the 10Base-T and 100Base-TX
CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The
ICS1893AG uses the same proven silicon as the
ICS1893AF but offers a smaller form factor solution to users
where physical package size is important.
All parametric specification and timing diagrams for the
ICS1893AF apply to the ICS1893AG. Refer to the
ICS1893AF datasheet for detailed specifications and timing.
The ICS1893AG uses the same twisted-pair transmit and
re cei ve circu its a s th e ICS 18 93 AF, an d th e s ame
recommended board layout techniques apply to the
ICS1893AG.
The ICS1893AG is intended for Node applications using the
standard MII interface to the MAC.
Features
•
Single 3.3 V ±10% power supply
•
Supports category 5 cables with attenuation in excess of
•
•
•
•
•
•
•
•
•
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•
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24dB at 100 MHz across a temperature range from 0°C to
+70°C. Industrial temperature version is also available.
DSP-based baseline wander correction to virtually
eliminate killer packets
Low-power, 0.35-micron CMOS (typically 400 mW)
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
10Base-T and 100Base-TX IEEE 802.3 compliant
Clock or crystal supported
Media Independent Interface (MII) supported
Managed or Unmanaged Applications
10M or 100M Half and Full Duplex Modes
Auto-Negotiation with Next Page. Parallel detection for
Legacy products
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Loopback mode for Diagnostic Functions
Small footprint 56-pin 240 mil TSSOP package.
ICS1893AG Block Diagram
100Base-TX
10/100 MII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
ICS1893AG, Rev. A 04/14/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
April, 2005
ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
Title
Page
Revision History
............................................................................................................................. 9
Chapter 1
Abbreviations and Acronyms ......................................................................................... 10
Chapter 2
Conventions and Nomenclature..................................................................................... 12
Chapter 3
Typical ICS1893AG Applications .................................................................................... 14
3.1
ICS1893AG / ICS1893AF Pin Differences.............................................................. 14
3.2
ICS1893AG / ICS1893AF Shared Features ........................................................... 15
Chapter 4
4.1
4.2
Chapter 5
5.1
5.1.1
5.1.2
5.2
5.3
5.4
5.5
5.6
5.7
Chapter 6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.5
Chapter 7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Overview of the ICS1893AG ............................................................................................ 16
100Base-TX Operation .......................................................................................... 17
10Base-T Operation ............................................................................................... 17
Operating Modes Overview............................................................................................. 18
Reset Operations ................................................................................................... 19
General Reset Operations ..................................................................................... 19
Specific Reset Operations ..................................................................................... 20
Power-Down Operations ........................................................................................ 21
Automatic Power-Saving Operations ..................................................................... 22
Auto-Negotiation Operations .................................................................................. 22
100Base-TX Operations ........................................................................................ 23
10Base-T Operations ............................................................................................. 23
Half-Duplex and Full-Duplex Operations ............................................................... 23
Interface Overviews.......................................................................................................... 24
MII Data Interface .................................................................................................. 25
Serial Management Interface ................................................................................. 26
Twisted-Pair Interface ............................................................................................ 26
Twisted-Pair Transmitter Interface ......................................................................... 27
Twisted-Pair Receiver Interface ............................................................................. 28
Clock Reference Interface ..................................................................................... 29
Status Interface ...................................................................................................... 31
Functional Blocks............................................................................................................. 33
Functional Block: Media Independent Interface ..................................................... 34
Functional Block: Auto-Negotiation ........................................................................ 35
Auto-Negotiation General Process ........................................................................ 36
Auto-Negotiation: Parallel Detection ...................................................................... 37
Auto-Negotiation: Remote Fault Signaling ............................................................. 37
Auto-Negotiation: Reset and Restart ..................................................................... 38
Auto-Negotiation: Progress Monitor ....................................................................... 38
ICS1893AG, Rev A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
2
April, 2005
ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.5.14
7.6
7.6.1
7.6.2
Title
Page
Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 40
PCS Sublayer ........................................................................................................ 40
PMA Sublayer ........................................................................................................ 40
PCS/PMA Transmit Modules ................................................................................. 41
PCS/PMA Receive Modules .................................................................................. 42
PCS Control Signal Generation ............................................................................. 43
4B/5B Encoding/Decoding ..................................................................................... 43
Functional Block: 100Base-TX TP-PMD Operations ............................................. 44
100Base-TX Operation: Stream Cipher Scrambler/Descrambler .......................... 44
100Base-TX Operation: MLT-3 Encoder/Decoder ................................................. 44
100Base-TX Operation: DC Restoration ................................................................ 44
100Base-TX Operation: Adaptive Equalizer .......................................................... 45
100Base-TX Operation: Twisted-Pair Transmitter ................................................. 45
100Base-TX Operation: Twisted-Pair Receiver ..................................................... 45
100Base-TX Operation: Auto Polarity Correction .................................................. 46
100Base-TX Operation: Isolation Transformer ...................................................... 46
Functional Block: 10Base-T Operations ................................................................ 47
10Base-T Operation: Manchester Encoder/Decoder ............................................. 47
10Base-T Operation: Clock Synthesis ................................................................... 47
10Base-T Operation: Clock Recovery ................................................................... 47
10Base-T Operation: Idle ....................................................................................... 48
10Base-T Operation: Link Monitor ......................................................................... 48
10Base-T Operation: Smart Squelch ..................................................................... 49
10Base-T Operation: Carrier Detection .................................................................49
10Base-T Operation: Collision Detection ............................................................... 49
10Base-T Operation: Jabber .................................................................................. 50
10Base-T Operation: SQE Test ............................................................................. 50
10Base-T Operation: Twisted-Pair Transmitter ..................................................... 51
10Base-T Operation: Twisted-Pair Receiver ......................................................... 51
10Base-T Operation: Auto Polarity Correction ....................................................... 51
10Base-T Operation: Isolation Transformer ........................................................... 51
Functional Block: Management Interface ............................................................... 52
Management Register Set Summary ..................................................................... 52
Management Frame Structure ............................................................................... 52
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
3
April, 2005
ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
Chapter 8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.4
Title
Page
Management Register Set ............................................................................................... 55
Introduction to Management Register Set ............................................................. 56
Management Register Set Outline ......................................................................... 56
Management Register Bit Access .......................................................................... 57
Management Register Bit Default Values .............................................................. 57
Management Register Bit Special Functions ......................................................... 58
Register 0: Control Register ................................................................................... 59
Reset (bit 0.15) ...................................................................................................... 59
Loopback Enable (bit 0.14) .................................................................................... 60
Data Rate Select (bit 0.13) ..................................................................................... 60
Auto-Negotiation Enable (bit 0.12) ......................................................................... 60
Low Power Mode (bit 0.11) .................................................................................... 61
Isolate (bit 0.10) ..................................................................................................... 61
Restart Auto-Negotiation (bit 0.9) .......................................................................... 61
Duplex Mode (bit 0.8) ............................................................................................. 62
Collision Test (bit 0.7) ............................................................................................ 62
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 62
Register 1: Status Register .................................................................................... 63
100Base-T4 (bit 1.15) ............................................................................................ 63
100Base-TX Full Duplex (bit 1.14) ......................................................................... 64
100Base-TX Half Duplex (bit 1.13) ........................................................................ 64
10Base-T Full Duplex (bit 1.12) ............................................................................. 64
10Base-T Half Duplex (bit 1.11) ............................................................................. 64
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 65
MF Preamble Suppression (bit 1.6) ....................................................................... 65
Auto-Negotiation Complete (bit 1.5) ....................................................................... 65
Remote Fault (bit 1.4) ............................................................................................ 66
Auto-Negotiation Ability (bit 1.3) ............................................................................ 66
Link Status (bit 1.2) ................................................................................................ 67
Jabber Detect (bit 1.1) ........................................................................................... 67
Extended Capability (bit 1.0) .................................................................................. 67
Register 2: PHY Identifier Register ........................................................................ 68
ICS1893AG, Rev A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
4
April, 2005
ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................ 70
OUI bits 19-24 (bits 3.15:10) .................................................................................. 70
Manufacturer's Model Number (bits 3.9:4) ............................................................. 71
Revision Number (bits 3.3:0) ................................................................................. 71
Register 4: Auto-Negotiation Register ................................................................... 72
Next Page (bit 4.15) ............................................................................................... 72
IEEE Reserved Bit (bit 4.14) .................................................................................. 72
Remote Fault (bit 4.13) .......................................................................................... 73
IEEE Reserved Bits (bits 4.12:10) ......................................................................... 73
Technology Ability Field (bits 4.9:5) ....................................................................... 74
Selector Field (Bits 4.4:0) ....................................................................................... 75
Register 5: Auto-Negotiation Link Partner Ability Register .................................... 76
Next Page (bit 5.15) ............................................................................................... 76
Acknowledge (bit 5.14) .......................................................................................... 77
Remote Fault (bit 5.13) .......................................................................................... 77
Technology Ability Field (bits 5.12:5) ..................................................................... 77
Selector Field (bits 5.4:0) ....................................................................................... 77
Register 6: Auto-Negotiation Expansion Register .................................................. 78
IEEE Reserved Bits (bits 6.15:5) ........................................................................... 78
Parallel Detection Fault (bit 6.4) ............................................................................. 79
Link Partner Next Page Able (bit 6.3) .................................................................... 79
Next Page Able (bit 6.2) ......................................................................................... 79
Page Received (bit 6.1) ......................................................................................... 79
Link Partner Auto-Negotiation Able (bit 6.0) .......................................................... 79
Register 7: Auto-Negotiation Next Page Transmit Register ................................... 80
Next Page (bit 7.15) ............................................................................................... 81
IEEE Reserved Bit (bit 7.14) .................................................................................. 81
Message Page (bit 7.13) ........................................................................................ 81
Acknowledge 2 (bit 7.12) ....................................................................................... 81
Toggle (bit 7.11) ..................................................................................................... 81
Message Code Field / Unformatted Code Field (bits 7.10:0) ................................. 81
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 82
Next Page (bit 8.15) ............................................................................................... 83
IEEE Reserved Bit (bit 8.14) .................................................................................. 83
Message Page (bit 8.13) ........................................................................................ 83
Acknowledge 2 (bit 8.12) ....................................................................................... 83
Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 83
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
5
April, 2005
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