A
DVANCED
L
INEAR
D
EVICES,
I
NC.
ALD310702A/ALD310702
PRECISION P-CHANNEL EPAD
®
MOSFET ARRAY
VGS(th)= -0.20V
QUAD NANOPOWER™ MATCHED PAIR
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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0.5% precision current mirrors and current sources
Low Tempco (<= 50ppm/°C) current mirrors/sources
Energy harvesting circuits
Very low voltage analog and digital circuits
Backup battery circuits & power failure detectors
Precision low level voltage-clamps
Low level zero-crossing detector
Source followers and buffers
Precision capacitive probes and sensor interfaces
Precision charge detectors and charge integrators
Discrete differential amplifier input stage
Peak-detectors and level-shifters
High-side switches and Sample-and-Hold switches
Precision current multipliers
Discrete analog switches / multiplexers
Discrete voltage comparators
e
TM
EPAD
E
N
®
AB
LE
D
GENERAL DESCRIPTION
ALD310702A/ALD310702 high precision monolithic quad P-Channel
MOSFET arrays are matched at the factory using ALD's proven EPAD
®
CMOS technology. This device is available in a quad version and is a
member of the EPAD
®
Matched Pair MOSFET Family. The
ALD310702A/ALD310702 is a P-channel version of the popular
ALD110802A/ALD110802 Precision Threshold device. Together, these
two MOSFET series enable complementary precision N-Channel and P-
Channel MOSFET array based circuits.
Intended for low voltage and low power small signal applications, the
ALD310702A/ALD310702 features precision -0.20V Gate Threshold
Voltage, which enables circuit designs with very low operating voltages
such as < +0.5V power supplies where the circuits operate below the
threshold voltage of the ALD310702A/ALD310702. This feature also
enhances input/output signal operating ranges, especially in very low
operating voltage environments. With these low threshold precision
devices, a circuit with multiple cascading stages can be constructed to
operate at extremely low supply or bias voltage levels. ALD310702A/
ALD310702 also features high input impedance (2.5 x 10
10
Ω)
and high
DC current gain (>10
8
).
ALD310702A/ALD310702 MOSFETs are designed for exceptional
matching of device electrical characteristics. The Gate Threshold Voltage
V
GS(th)
is set precisely at -0.20V +/-0.02V, featuring a typical offset
voltage of only +/-0.001V (1mV). As these devices are on the same
monolithic chip, they also exhibit excellent temperature tracking
characteristics. They are versatile design components for a broad range
of precision analog applications such as basic building blocks for current
mirrors, matching circuits, current sources, differential amplifier input
stages, transmission gates, and multiplexers. These devices also excel
in limited operating voltage applications such as very low level precision
voltage-clamps. In addition to matched pair electrical characteristics,
each individual MOSFET exhibits individual well controlled manufacturing
characteristics, enabling the user to depend on tight design limits from
different production batches.
(Continued on next page)
FEATURES & BENEFITS
• Precision matched Gate Threshold Voltages
• Precision offset voltages (V
OS
):
ALD310702A: 2mV max.
ALD310702: 10mV max.
• Sub-threshold voltage operation
• Low min. operating voltage of less than 0.2V
• Ultra low min. operating current of less than 1nA
• Nano-power operation
• Wide dynamic operating current ranges
• Exponential operating current ranges
• Matched transconductance and output conductance
• Matched and tracked temperature characteristics
• Tight lot-to-lot parametric control
• Positive, zero, and negative V
GS(th)
tempco bias currents
• Low input capacitance
• Low input/output leakage currents
BLOCK DIAGRAM
V- (5)
D
P1
(2)
D
P2
(15)
PIN CONFIGURATION
ALD310702
IC1*
D
P3
(11)
D
P4
(6)
1
2
3
4
5
6
7
8
SCL, PCL PACKAGES
16
M1
M2
15
14
13
12
M4
M3
11
10
9
IC2*
DP2
GP2
SP2
V
+
DP3
GP3
SP3
~
DP1
G
P4
(7)
G
P1
(3)
G
P2
(14) G
P3
(10)
I
C1
(1) I
C2
(16)
+
S
P1
(4) V (12) S
P2
(13)
V-
V-
S
P3
(9)
GP1
SP1
V
-
DP4
V+ (12)
S
P4
(8)
ORDERING INFORMATION
(“L” suffix
denotes lead-free (RoHS))
Operating Temperature Range *
0°C to +70°C
16-Pin SOIC Package
ALD310702ASCL
ALD310702SCL
16-Pin Plastic Dip Package
ALD310702APCL
ALD310702PCL
GP4
SP4
*IC pins are internally connected, connect to V-
*Contact factory for industrial temp. range or user-specified threshold voltage values.
©2017 Advanced Linear Devices, Inc., Vers. 1.1
www.aldinc.com
1 of 9
GENERAL DESCRIPTION (cont.)
These devices are built to offer minimum offset voltage and differential
thermal response, and they can also be used for switching and
amplifying applications in -0.40V to -8.0V (+/-0.20V to +/-4.0V)
powered systems where low input bias current, low input capacitance,
and fast switching speed are desired. These devices, exhibiting well
controlled turn-off and sub-threshold characteristics, operate the
same as standard enhancement mode P-Channel MOSFETs.
However, the precision of the Gate Threshold Voltage enable two
key additional characteristics, or operating features. First, the
operating current level varies exponentially with gate bias voltage at
or below the Gate Threshold Voltage (subthreshold region). Second,
the circuit can be biased and operated in the subthreshold region
with nA of bias current and nW of power dissipation.
For most general applications, connect the V+ pin to the most
positive voltage and the V- and IC (internally-connected) pins to the
most negative voltage in the system. All other pins must have
voltages within these voltage limits at all times. Standard ESD
protection facilities and procedures for static sensitive devices are
required when handling these devices.
ABSOLUTE MAXIMUM RATINGS
Drain-Source voltage, V
DS
-8.0V
Gate-Source voltage, V
GS
-8.0V
Operating Current
80mA
Power dissipation
500mW
Operating temperature range SCL, PCL
0°C to +70°C
Storage temperature range
-65°C to +150°C
Lead temperature, 10 seconds
+260°C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
OPERATING ELECTRICAL CHARACTERISTICS
V+ = +5V V- = GND TA = 25
°
C unless otherwise specified
ALD310702A
Parameter
Gate Threshold
Voltage
Offset Voltage
Symbol
VGS(th)
VOS
TCVGS(th)
IDS(ON)
GFS
Min
-0.22
Typ
-0.20
Max
-0.18
Min
-0.22
ALD310702
Typ
-0.20
Max
-0.18
Unit
V
Test Conditions
IDS = -1µA, VDS = -0.1V
VGS(th)M1 - VGS(th)M2 or
VGS(th)M3 - VGS(th)M4
1
2
2
10
mV
Gate Threshold
Temperature
Drain Source On
Current
Transconductance
Current
2
Transconductance
Mismatch
Output Conductance
2
-2
-2
mV/°C
-2.03
-2.03
mA
VGS = VDS = -5.0V
VGS = VDS = -5.0V
VGS = VDS = -5.0V
570
570
µA/V
∆G
FS
1
1
%
GOS
RDS(ON)
48
48
µA/V
VGS(th) = -4.0V,
VDS = -5.0V
VGS = -5.0V,
VDS = -0.1V
Drain Source On
Resistance
Drain Source On
Resistance Mismatch
Drain Source
Breakdown
Drain Source
Leakage Current
1
Gate Leakage Current
1.14
1.14
KΩ
∆R
DS(ON)
1
1
%
BVDSX
IDS (OFF)
-8.0
-8.0
V
400
400
pA
IGSS
CISS
2.5
200
200
pA
Input Capacitance
2
2.5
pF
Notes:
1
2
Consists of junction leakage currents
Sample tested parameters
ALD310702A/ALD310702, Vers. 1.1
Advanced Linear Devices, Inc.
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