NCL30060
High PF Offline Single Stage
LED Driver with High
Voltage Startup
The NCL30060 is a switch mode power supply controller intended
for low to medium power single stage power factor (PF) corrected
LED Drivers. It employs a constant on−time control method to ensure
near unity power factor across a wide range of input voltages and
output power. It can be used for isolated flyback as well as buck
topologies. The device offers a suite of robust protection features to
ensure safe operation under a range of fault conditions.
Version NCL30060B2 is intended for constant voltage (CV)
regulated output drivers where a DC−DC converter or linear regulator
in the second stage controls the current to the LEDs so the output short
circuit protection detector function has been disabled. Version
NCL30060B3 is intended for applications not requiring Brown Out
protection or output short circuit protection as typical with low
standby operation. The NCL30060B4 removes on−time modulation
for solutions not needing this feature.
Features
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MARKING
DIAGRAM
8
SOIC−7
CASE 751U
L0060xx
ALYWG
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Built−In High Voltage Start−up Circuit
Direct Opto−coupler Feedback Connection
Constant On−Time PWM Control
Quasi−Resonant Switching
Low Operating Current (1.6 mA typical)
Source 250 mA / Sink 400 mA Totem Pole Gate Driver
Integrated 12 V (typ) Gate Drive Clamp
Frequency Dithering for Reduced EMI Profile
Enable/Disable Function
Dynamic Self−Supply (DSS) Operation
Operating T
J
from
−40°C
to 105°C
Maximum On Time Protection
Integrated Brown−out
Overvoltage Protection
Cycle−by−Cycle Overcurrent Protection
Output Winding Short−Circuit Protection
Thermal Shutdown
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
L0060xx = Specific Device Code
xx
= A, B, B1, B2, B3, B4
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
FB 1
CS/ZCD 2
RT 3
GND
4
(Top View)
6
5
VCC
DRV
8
HV
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
Typical Applications
•
LED Lighting
©
Semiconductor Components Industries, LLC, 2016
April, 2018
−
Rev. 8
1
Publication Order Number:
NCL30060/D
Cclamp
Rclamp
Cout +
Line
EMI FILTER
Cin
Dout
LED Anode
RVout1
Neutral
RVcc1
Rcomp2
Dclamp
Ccomp1
DZCD
DHV
DVcc
U3
NCP4328A
FBC
VSNS
Vcc
GND
ISNS
Ccomp2
NCL30060
4
3
CFB
RT
CVcc
Rsense
2
Figure 1. NCL30060 Typical Application Diagram
1
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RZCD
U1
NCL30060
FB
HV
Vcc
DRV
U2
M1
CS
RT
GND
RCS
CY
2
CVcc1
Ro
DVcc1
RIS1
RVout2
RIS
LED Cathode
NCL30060
Auto−Restart
Fault Control
Open RT Pin
I
start
Selector
Brown−out
Detection
‘HV Tran
BO_NOK
Short Circuit Detector
Integration
Pulse
ACTIVE
Thermal
Shutdown
HV
Delay
t
SHDN(delay)
TSHDN
Central
Logic
VCC_OK
Counter
Count
Reset
t
int
Maximum
Off−Time
Detector
t
off(MAX)
DRV
VCC
Internal
Reference
V
DD2
V
DD
ACTIVE
UVLO
Startup
Control
blanking
(Fault_OVP)
DRV
Counter
Count
DRV
Reset
Edge
Detector
TSHDN
ZCD Blanking
Time
S
Q
Reset
Dominant
Latch
Q
R
Max On Time
Comparator
V
ton(MAX)
FB
PWM DRV
Comparator
FB Offset
On Time
Ramp
Max On−Time
Clamp
ACTIVE
I
RT
Current
Mirror
+
V
PRT
−
DRV
V
CC
Clamp
ACTIVE
UVLO
DRV
GND
V
DD2
Von−time
Ramp Modulation
f
MOD
t
on(mod)
DRV
ACTIVE
Figure 2. NCL30060 Internal Functional Block Diagram
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3
+
−
−
t
disable(blank)
/
t
enable(blank)
+
Delay
RT Disable
Comparator
R
CS
RT Enable
Comparator
V
RT(enable)
I
RT(disable)
* R
CS
−
HV(high)
+
Disable
Selector
Reset
Re−start
ILIM2, OVP
DRV
Edge
Detector
−
ILIM2
+
−
t
off1,2
Timer
Short
Winding
Comparator
+
V
CC(on)
/
V
CC(off)
/
V
CC(reset)
/
V
CC(rUVLO)
/
V
CC(OVP)
V
ILIM1
LEB
t
CS(LEB2)
V
ILIM2
UVLO
ZCD
Comparator
+
V
CC
CS/ZCD
V
CC
V
ZCD
RT
−
VCC
Management
OVP
Comparator
V
OVP
Peak Current
DRV Comparator
LEB
t
CS(LEB1)
+
−
NCL30060
Table 1. NCL30060 PIN FUNCTION DESCRIPTION
Pin No
1
2
Pin Name
FB
CS/ZCD
Pin Description
Feedback Input. The FB pin is the control input to the PWM comparator. A voltage level controlled by the
feedback loop on this pin is compared to the internal ramp establishing power switch on time.
Current sense and zero current detection. The CS input is used to sense the instantaneous switch cur-
rent in the external power switch during switch on time. A fast−responding high threshold level for short
circuit detection is provided along with a longer blanking time at lower level for overload conditions. Dur-
ing switch off time, this pin monitors the bias winding to detect transformer demagnetization. When
stored energy is depleted the gate drive turns on the power switch initiating the next cycle. This pin also
detects overvoltage conditions through the bias winding. A blanking time prevents false overvoltage trig-
gering due to noise.
Maximum on−time adjust. The RT pin establishes the ramp charging current. The PWM comparator es-
tablishes the switch on time from the ramp and FB signal. Pulling the RT pin below the disable threshold
forces the controller in the Armed mode where all switching functions cease.
Ground. This is the ground reference for the controller. All bypassing and control components should be
connected to the GND pin with a short trace length to minimize noise.
Drive. The high current capability of the totem pole gate drive makes it suitable to directly control high
gate charge power MOSFETs. The driver stage provides both passive and active pull−down circuits
which force the MOSFET gate off when VCC is below normal operating levels.
IC Supply. This is the positive supply of the controller and source for powering external circuits. Internal
bias will be disabled when external power is sufficient to maintain operation.
No−connect. This missing pin provides creepage distance.
High−voltage input. Monitors input voltage for brown−out detection and power to operate controller.
3
RT
4
5
GND
DRV
6
7
8
VCC
NC
HV
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4
NCL30060
Table 2. MAXIMUM RATINGS
(Notes 1, 2, 3 and 4)
Rating
FB Voltage
FB Current
CS/ZCD Voltage
CS/ZCD Current
RT Voltage
RT Current
DRV Voltage (Note 2)
DRV Sink Current
DRV Source Current
Supply Voltage
Supply Voltage Rate of Change
Supply Current
HV Voltage
HV Current
Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)
ESD Capability
Human Body Model per JEDEC Standard JESD22−A114E. (Note 5)
Machine Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
Operating Temperature Range While Biased
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
T
J
T
JMax
T
STG
T
L
Symbol
V
FB
I
FB
V
CS/ZCD
I
CS/ZCD
V
RT
I
RT
V
DRV
I
DRV(sink)
I
DRV(source)
V
CC
dV
CC
/dt
I
CC
V
HV
I
HV
R
qJA
Value
−0.3
to 10
±10
−0.9
to 12.4
−2
/ +5
−0.3
to 5
±10
−0.3
to V
DRV(high)
400
250
−0.3
to 30
1
20
−0.3
to 700
20
125
5000
200
1500
−40
to 105
150
−60
to 150
300
Unit
V
mA
V
mA
V
mA
V
mA
mA
V
V/ms
mA
V
mA
_C/W
V
°C
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
CS/ZCD(MAX)
is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 7.4 V, the pin sinks a
current equal to [(V
CS/ZCD
−
7.4 V) / 1 kW]. A V
CS/ZCD
of 9 V generates a sink current of approximately 1.6 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, V
DRV(high)
, when V
CC
exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is V
CC
.
3. This device contains Latch−Up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds
±100
mA.
4. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm
2
of 2 oz copper trances and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
5. Pin 8 HV pin is ESD rated to 1200 V.
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