19-6032; Rev 9/11
DS1672
I
2
C 32-Bit Binary Counter RTC
GENERAL DESCRIPTION
The DS1672 incorporates a 32-bit counter and
power-monitoring functions. The 32-bit counter
is designed to count seconds and can be used to
derive time-of-day, week, month, month, and
year by using a software algorithm. A precision,
temperature-compensated
reference
and
comparator circuit monitors the status of V
CC
.
When an out-of-tolerance condition occurs, an
internal power-fail signal is generated that forces
the reset to the active state. When V
CC
returns to
an in-tolerance condition, the reset signal is kept
in the active state for a period of time to allow
the power supply and processor to stabilize.
FEATURES
32-Bit Counter
I
2
C Serial Interface
Automatic Power-Fail Detect and Switch
Circuitry
Power-Fail Reset Output
Low-Voltage Oscillator Operation
(1.3V min)
Trickle-Charge Capability
Underwriters Laboratories (UL) Recognized
-40°C to +85°C Operating Range
PIN CONFIGURATION
TOP VIEW
X1
X2
V
BACKUP
GND
1
2
3
4
8
7
6
5
V
CC
RST
SCL
SDA
TYPICAL OPERATING CIRCUIT
DS1672
PDIP
SO
µSOP
.
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DS1672
ORDERING INFORMATION
PART
DS1672-2+
DS1672-3+
DS1672-33+
DS1672S-2+
DS1672S-3+
DS1672S-33+
DS1672S-3+T&R
DS1672S-33+T&R
DS1672U-2+
DS1672U-3+
DS1672U-33+
DS1672U-33+T&R
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VOLTAGE (V) PIN-PACKAGE
2.0
3.0
3.3
2.0
3.0
3.3
3.0
3.3
2.0
3.0
3.3
3.3
8 PDIP (300 mils)
8 PDIP (300 mils)
8 PDIP (300 mils)
8 SO (150 mils)
8 SO (150 mils)
8 SO (150 mils)
TOP MARK*
DS1672-2
DS1672-3
DS1672-33
D1672-2
D1672-3
D167233
8 SO (150 mils)/Tape
D1672-3
and Reel
8 SO (150 mils)/Tape
D167233
and Reel
1672
8
µSOP(3mm)
rr -2
1672
8
µSOP(3mm)
rr -3
1672
8
µSOP(3mm)
rr -33
8
µSOP(3mm)/Tape
1672
rr -33
and Reel
+
Denotes a lead-free/RoHS-compliant device.
*
A “+” anywhere on the top mark denotes a lead-free device. rr = 2-digit alphanumeric revision code.
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DS1672
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +6.0V
Operating Temperature Range (noncondensing) ...…………………………………………-40°C to +85°C
Storage Temperature Range……………………………………………………………….-55°C to +125°C
Soldering Temperature (reflow)………………………………………….………………….
+260°C
Lead Temperature (soldering, 10s) ……………………………………………………………….. +260°C
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
(T
A
= -40°C to +85°C) (Note 1)
PARAMETER
DS1672-2
Supply
DS1672-3
Voltage
DS1672-33
Logic 1
Logic 0
Backup Supply Voltage
Note 1:
All voltages referenced to ground.
SYMBOL
V
CC
V
CC
V
CC
V
IH
V
IL
V
BACKUP
MIN
1.8
2.7
2.97
0.7 x V
CC
-0.5
1.3
TYP
2.0
3.0
3.3
3.0
MAX
5.5
5.5
5.5
V
CC
+ 0.5
+0.3 x V
CC
3.63
UNITS
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
(V
CCMIN
< V
CC
< V
CCMAX,
T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Active Supply Current
(Note 2)
Standby Current
(Note 3)
Power-Fail Voltage
SYMBOL
CONDITIONS
I
CCA
-2: V
CC
= 2.2V
-3: V
CC
= 3.3V
-33: V
CC
= 3.63V
I
CCS
-2: V
CC
= 2.2V
-3: V
CC
= 3.3V
-33: V
CC
= 3.63V
V
PF
-2:
-3:
-33:
I
BACKUPLKG
I
OL
V
OL
= 0.4V
I
OL
V
CC
> 2V; V
OL
= 0.4V
V
CC
< 2V; V
OL
= V
CC
* 0.2
MIN
TYP
MAX
600
UNITS
µA
500
µA
2.70
2.45
1.58
V
BACKUP
Leakage Current
Logic 0 Output (Note 4)
Logic 0 Output (Note 4,
DS1672-2 Only)
2.88
2.60
1.70
25
2.97
2.70
1.80
50
3
3
V
nA
mA
mA
Note 1:
All voltages referenced to ground.
Note 2:
I
CCA
specified with SCL clocking at max frequency (400kHz), trickle charger disabled.
Note 3:
I
CCS
specified with V
CC
= V
CCTYP
and SDA, SCL = V
CCTYP
, trickle charger disabled.
Note 4:
SDA and
RST.
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DS1672
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40°C to +85°C.) (Note 5)
PARAMETER
V
BACKUP
Current (Oscillator On)
V
BACKUP
Current (Oscillator Off)
SYMBOL
I
BACKUPOSC
I
BACKUP
MIN
TYP
0.425
MAX
1
200
UNITS
µA
nA
Note 5:
Using the recommended crystal on X1 and X2.
CRYSTAL SPECIFICATIONS
*
PARAMETER
Nominal Frequency
Series Resistance
Load Capacitance
SYMBOL
f
O
ESR
C
L
MIN
TYP
32.768
6
MAX
45
UNITS
kHz
kΩ
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal
Considerations for Dallas Real-Time Clocks
for additional specifications
4 of 15
DS1672
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40°C to +85°C.)
PARAMETER
SCL Clock
Frequency
Bus Free Time
Between a STOP and
START Condition
Hold Time
(Repeated) START
Condition (Note 6)
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time
(Notes 7, 8)
Data Setup Time
(Note 9)
Rise Time of Both
SDA and SCL
Signals (Note 10)
Fall Time of Both
SDA and SCL
Signals (Note 10)
Setup Time for STOP
Condition
Capacitive Load for
Each Bus Line
(Note 10)
I/O Capacitance
SYMBOL
f
SCL
Standard mode
Fast mode
t
BUF
Standard mode
Fast mode
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
t
SU:DAT
t
R
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
t
F
Standard mode
Fast mode
t
SU:STO
Standard mode
0.6
4.0
400
10
20 + 0.1C
B
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C
B
300
1000
300
300
ns
µs
ns
ns
0.9
100
µs
µs
µs
µs
µs
µs
CONDITIONS
Fast mode
MIN
100
TYP
MAX
400
kHz
UNITS
t
HD:DAT
C
B
C
I/O
pF
pF
Note 6:
After this period, the first clock pulse is generated.
Note 7:
A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
IHMIN
of the SCL signal) in
order to bridge the undefined region of the falling edge of SCL.
Note 8:The
maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R
max + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL
line is released.
Note 10:
C
B
–Total capacitance of one bus line in pF.
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