Handling Notes for Clock Oscillators
1. Shock & Drop • Vibration
Do not inflict excessive shock and mechanical vibration that
exceeds the norm, such as hitting or mistakenly dropping,
when transporting and mounting on a board. There are cases
when pieces of crystal break, and pieces that are used become
damaged, and become inoperable. When a shock or vibration
that exceeds the norm has been inflicted, make sure to check the
characteristics.
2. Cleaning
Since a crystal piece can be broken by resonance when a crystal
device is cleaned by ultrasonic cleaning, be careful when carrying
out ultrasonic cleaning.
3. Soldering conditions
To maintain the product reliability, please follow recommended conditions.
Standard soldering iron conditions
Clock Oscillators
Soldering iron
Time
280
°
C to 340
°
C
3
+
1/
−
0 sec. max.
Reflow conditions (Example)
0
Peak: 260
10
C
10 sec. max.
Temperature ( C)
180
0
10
C
230 C min.
40 sec. max.
120 sec. max.
Time (sec.)
Clock Oscillators
Recommended reflow Conditions vary depending upon products.
Please check with the respective specification for details.
4. Mounting Precautions
The lead of the device and the pattern of the board is soldered on the surface. Since extreme deformation of the board tears off the pattern,
tears off the lead metal, cracks the solder and damages the sealed part of the device and there are cases in which performance deteriorates
and operation fails, use it within the stipulated bending conditions. Due to the small cracks in the board resulting from mounting, please pay
sufficient attention when attaching a device at the position where the warping of the board is great.
When using an automatic loading machine, as far as possible, select a type that has a small impact and use it while confirming that there is
no damage.
Surface mount devices are NOT flow soldering compatible.
5. Storage Condition
Since the long hour high temperature and low temperature storage, as well as the storage at high humidity are causes of deterioration in
frequency accuracy and solderability.
Parts should be stored in temperature range of
−
5 to
+
40
°
C, humidity 40 to 60% RH, and avoid direct sunlight. Then use within 6 months.
As of March 2018
Handling Notes for Clock Oscillators
6. In order to use clock oscillators
(1) The miniature oscillator for the clock utillzes a CMOS IC and incorporates a protective circuit against static electricity. However, exercise
care in the same manner as for a normal CMOS IC.
(2) Internal capacitor is not provided in the power supply section (
+
DC-GND).
*
To serve as overimpressed voltage and overcurrent protective device, place a bypass capacitor (0.01
μ
F) as near as possible to the (
+
DC-GND)
terminal. However, the capacitance value is meant as a guideline. Depending on the capacitor type, frequency characteristics vary. Accordingly,
use a capacitor that matches the frequency characteristics.
*
KC7050S series has Bypass Capacitior between V
CC
and GND.
(3) Applying reverse voltage could result in damage to internal parts. Take care not to connect terminals incorrectly.
(4) Please do not use oscillators under unfavorable condition such as beyond specified range in catalog or specification sheet.
(5) Please keep oscillators away from water, salt water or harmful gas.
(6) KC7050S series should be stored in humidity-controlled area after the package is unsealed, in temperature
+
25
±
5
°
C, under humidity of
65%RH, and should be mounted on PCB within 7 days.
Clock Timing Chart
[CMOS Output]
[LV-PECL (3.3V) Output]
Tr
Tr
V
CC
V
OH
90% V
CC
Tf
Output
V
OH
Tf
2.420V
2.275V
80% Waveform
Crossing Point
20% Waveform
1.680V
1.490V
T
1
T
0
1/ F
OUT
Symmetry T
1
/ T
0
100 (%)
T
0
1/ F
OUT
Symmetry T
1
/ T
0
100 (%)
50% V
CC
V
OL
GND
T
1
10% V
CC
Output
V
OL
[LV-PECL (2.5V) Output]
Tr
Output
V
OH
Tf
[LVDS Output]
Tr
1.760V
1.475V
80% Waveform
Crossing Point
20% Waveform
1.095V
0.690V
T
1
T
0
1/ F
OUT
Symmetry T
1
/ T
0
100 (%)
Output
V
OH
Tf
80% Waveform
Crossing Point
20% Waveform
Output
V
OL
T
1
T
0
1/ F
OUT
Symmetry T
1
/ T
0
100 (%)
Output
V
OL
[HCSL-Output]
Tr
Output
0.60V
0.525V
Crossing Point
0.175V
0.15V
Output
T
1
T
0
1/ F
OUT
Symmetry T
1
/ T
0
100
％）
（
-0.15V
Tf
0.85V
Voh
Vol
As of March 2018
Handling Notes for Clock Oscillators
Test Circuits
CMOS Output Test Circuits
A
Pad4
Pad3
A
Oscillator
Pad1
Power
Supply
V
0.01 F
INH
Pad2
CL
3.3V
V
10 F
0.01 F
①
②
③
⑥
⑤
④
50ohm
Oscillator
50ohm
Test Point
HCSL Output Test Circuits
Z0 50ohm
E/ D Control
Note) Maximum load (Includes capacitances of fixture and probe)
LV-PECL (3.3V/ XO) Output Test Circuits
Z0 50ohm
ECL Termination
Test Point1
ECL
LV-PECL (2.5V/ XO) Output Test Circuits
Z0 50ohm
ECL Termination
Test Point1
ECL
Z0 50ohm
A
⑥
⑤
Oscillator
3.3V
V
10 F
0.01 F
①
②
③
④
ECL Termination
Test Point2
ECL
Z0 50ohm
A
⑥
⑤
Oscillator
④
ECL Termination
Test Point2
ECL
BIAS V
CC
2.0V
2.5V
V
10 F
0.01 F
①
②
③
BIAS V
CC
2.0V
E/ D Control
E/ D Control
LVDS (3.3V/ XO) Output Test Circuits
RL
⑥
⑤
Oscillator
3.3V
V
10 F 0.01 F
①
②
③
V
OH
V
OS
,
,dV
OS
V
OS
dV
OS
V
OL
INH
④
RL
LVDS (2.5V/ XO) Output Test Circuits
RL
⑥
⑤
Oscillator
2.5V
V
10 F 0.01 F
①
②
③
V
OH
V
OS
,
,dV
OS
V
OS
dV
OS
V
OL
INH
④
RL
A
V
OD
,dV
OD
V
OD
, dV
OD
Duty,Vopp,Tr/Tf
Tf
Duty, Vopp, Tr/
A
V
OD
,dV
OD
V
OD
, dV
OD
Duty,Vopp,Tr/Tf
Tf
Duty, Vopp, Tr/
Note) RL=50
Note) RL=50
CMOS (VCXO 4pad) Output Test Circuits
A
Pad4
Pad3
Test Point
CMOS (VCXO 6pad) Output Test Circuits
A
⑥
⑤
Oscillator
④
Test Point
Oscillator
Pad1
Power
Supply
V
0.01 F
Power
Supply
(V
C
)
V
Pad2
CL
Power
Supply
V
0.01 F
Power
Supply
(V
C
)
①
②
③
CL
V
INH
Note) Maximum load (Includes capacitances of fixture and probe)
Note) Maximum load (Includes capacitances of fixture and probe)
As of March 2018
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
