BCM53DS
10 April 2018
80 V, 1 A PNP/PNP matched double transistors
Product data sheet
1. General description
PNP/PNP matched double transistors in a small SOT457 (SC-74) Surface-Mounted Device (SMD)
plastic package.
NPN/NPN complement: BCM56DS
2. Features and benefits
•
•
•
•
•
•
High collector current capability I
C
and I
CM
Reduces component count
Reduces pick and place costs
Current gain matching 5%
Application-optimized pinout
AEC-Q101 qualified
3. Applications
•
•
•
•
•
•
•
Current mirror
Differential amplifier
Linear voltage regulators
MOSFET drivers
High-side switches
Power management
Amplifiers
4. Quick reference data
Table 1. Quick reference data
Symbol
Per transistor
V
CEO
I
C
I
CM
h
FE
Per device
h
FE1
/h
FE2
DC current gain
matching
V
CE
= -5 V; I
C
= -2 mA; T
amb
= 25 °C
0.95
1
1.05
collector-emitter
voltage
collector current
peak collector current
DC current gain
single pulse; t
p
≤ 1 ms
V
CE
= -2 V; I
C
= -150 mA; T
amb
= 25 °C
[1]
open base
-
-
-
63
-
-
-
-
-80
-1
-2
250
V
A
A
Parameter
Conditions
Min
Typ
Max
Unit
Nexperia
BCM53DS
80 V, 1 A PNP/PNP matched double transistors
Symbol
V
BE1
−V
BE2
[1]
[2]
Parameter
base-emitter voltage
matching
Conditions
[2]
Min
-
Typ
-
Max
2
Unit
mV
Pulse test: t
p
≤ 300 μs; δ ≤ 0.02
The smaller of the two values is subtracted from the larger value.
5. Pinning information
Table 2. Pinning information
Pin
1
2
3
4
5
6
Symbol Description
B1
B2
C2
E2
E1
C1
base TR1
base TR2
collector TR2
emitter TR2
emitter TR1
collector TR1
1
2
3
B1
B2
C2
aaa-024630
Simplified outline
6
5
4
Graphic symbol
C1
TR1
TR2
E1
E2
TSOP6 (SOT457)
6. Ordering information
Table 3. Ordering information
Type number
BCM53DS
Package
Name
TSOP6
Description
plastic, surface-mounted package (SC-74)
Version
SOT457
7. Marking
Table 4. Marking codes
Type number
BCM53DS
Marking code
3C
BCM53DS
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
10 April 2018
2 / 13
Nexperia
BCM53DS
80 V, 1 A PNP/PNP matched double transistors
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC60134).
Symbol
Per transistor
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
Blim
I
BM
P
tot
Per device
P
tot
T
j
T
amb
T
stg
[1]
[2]
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
collector current
peak collector current
limiting base current
peak base current
total power dissipation
Conditions
open emitter
open base
open collector
single pulse; t
p
≤ 1 ms
single pulse; t
p
≤ 1 ms
T
amb
≤ 25 °C
[1]
[2]
Min
-
-
-
-
-
-
-
-
-
-
-
-
-55
-65
Max
-100
-80
-5
-1
-2
-0.2
-0.3
270
320
400
500
150
150
150
Unit
V
V
V
A
A
A
A
mW
mW
mW
mW
°C
°C
°C
total power dissipation
junction temperature
ambient temperature
storage temperature
T
amb
≤ 25 °C
[1]
[2]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
2
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated; mounting pad for collector 1 cm .
600
P
tot
(mW)
400
aaa-027468
(1)
(2)
200
0
-75
-25
2
25
75
125
175
T
amb
(°C)
(1) = FR4 PCB, single sided copper, 1 cm
(2) = FR4 PCB, single sided copper, standard footprint
Fig. 1.
Per device: Power derating curves
BCM53DS
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
10 April 2018
3 / 13
Nexperia
BCM53DS
80 V, 1 A PNP/PNP matched double transistors
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Per transistor
R
th(j-a)
thermal resistance
from junction to
ambient
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
in free air
[1]
[2]
in free air
[1]
[2]
-
-
-
-
-
-
463
391
150
K/W
K/W
K/W
Parameter
Conditions
Min
Typ
Max
Unit
R
th(j-sp)
Per device
R
th(j-a)
-
-
-
-
313
250
K/W
K/W
[1]
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm .
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.50
0.33
0.20
0.10
0.05
10
0.02
aaa-027469
0.01
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, single sided copper, tin-plated and standard footprint
Fig. 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
BCM53DS
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
10 April 2018
4 / 13
Nexperia
BCM53DS
80 V, 1 A PNP/PNP matched double transistors
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.33
0.20
0.10
0.05
10 0.02
0.01
0.50
aaa-027470
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
2
10
10
2
t
p
(s)
10
3
FR4 PCB, single sided copper, tin-plated, mounting pad for collector 1 cm
Fig. 3.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
BCM53DS
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
10 April 2018
5 / 13
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