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74AUP2G00GN,115

Description
IC GATE NAND 2CH 2-INP 8XSON
Categorylogic    logic   
File Size249KB,22 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric Compare View All

74AUP2G00GN,115 Overview

IC GATE NAND 2CH 2-INP 8XSON

74AUP2G00GN,115 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeSON
package instructionSON,
Contacts8
Manufacturer packaging codeSOT1116
Reach Compliance Codecompliant
Samacsys Description74AUP2G00 - Low-power dual 2-input NAND gate@en-us
seriesAUP/ULP/V
JESD-30 codeR-PDSO-N8
JESD-609 codee3
length1.2 mm
Logic integrated circuit typeNAND GATE
Humidity sensitivity level1
Number of functions2
Number of entries2
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)24.9 ns
Maximum seat height0.35 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.3 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width1 mm
Base Number Matches1
74AUP2G00
Rev. 10 — 3 July 2017
Low-power dual 2-input NAND gate
Product data sheet
1
General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5 000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; I
CC
= 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP2G00GN,115 Related Products

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Description IC GATE NAND 2CH 2-INP 8XSON IC GATE NAND 2CH 2-INP 8XSON IC GATE NAND 2CH 2-INP 8XSON IC GATE NAND 2CH 2-INP 8XQFN IC GATE NAND 2CH 2-INP 8X2SON IC GATE NAND 2CH 2-INP 8XSON IC GATE NAND 2CH 2-INP 8XSON IC GATE NAND 2CH 2-INP 8VSSOP NAND Gate, AUP/ULP/V Series, 2-Func, 2-Input, CMOS, PDSO8
Maker Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction SON, VSON, SOLCC8,.11,20 SON-8 QFN-8 HVBCC, SON-8 VSON, VSSOP-8 VSSOP,
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant
series AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 code R-PDSO-N8 R-PDSO-N8 R-PDSO-N8 S-PQCC-N8 R-PBCC-B8 R-PDSO-N8 R-PDSO-N8 R-PDSO-G8 R-PDSO-G8
length 1.2 mm 3 mm 1.35 mm 1.6 mm 1.35 mm 1.35 mm 1.95 mm 2.3 mm 2.3 mm
Logic integrated circuit type NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE
Number of functions 2 2 2 2 2 2 2 2 2
Number of entries 2 2 2 2 2 2 2 2 2
Number of terminals 8 8 8 8 8 8 8 8 8
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SON VSON VSON VQCCN HVBCC VSON VSON VSSOP VSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR SQUARE RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE CHIP CARRIER, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 24.9 ns 24.9 ns 24.9 ns 24.9 ns 24.9 ns 24.9 ns 24.9 ns 24.9 ns 24.9 ns
Maximum seat height 0.35 mm 0.5 mm 0.35 mm 0.5 mm 0.35 mm 0.5 mm 0.5 mm 1 mm 1 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V
Nominal supply voltage (Vsup) 1.1 V 1.1 V 1.1 V 1.2 V 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V
surface mount YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD BUTT NO LEAD NO LEAD GULL WING GULL WING
Terminal location DUAL DUAL DUAL QUAD BOTTOM DUAL DUAL DUAL DUAL
width 1 mm 2 mm 1 mm 1.6 mm 0.8 mm 1 mm 1 mm 2 mm 2 mm
Brand Name Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia -
Parts packaging code SON SON SON QFN - SON SON SSOP -
Contacts 8 8 8 8 - 8 8 8 -
Manufacturer packaging code SOT1116 SOT996-2 SOT1203 SOT902-2 SOT1233 SOT1089 SOT833-1 SOT765-1 -
Samacsys Description 74AUP2G00 - Low-power dual 2-input NAND gate@en-us - 74AUP2G00 - Low-power dual 2-input NAND gate@en-us 74AUP2G00 - Low-power dual 2-input NAND gate@en-us - 74AUP2G00 - Low-power dual 2-input NAND gate@en-us 74AUP2G00 - Low-power dual 2-input NAND gate@en-us 74AUP2G00 - Low-power dual 2-input NAND gate@en-us -
JESD-609 code e3 e4 e3 e4 - e3 e3 e4 -
Humidity sensitivity level 1 1 1 1 - 1 1 1 -
Peak Reflow Temperature (Celsius) NOT SPECIFIED 260 NOT SPECIFIED 260 NOT SPECIFIED NOT SPECIFIED 260 260 -
Terminal surface Tin (Sn) NICKEL PALLADIUM GOLD Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) - Tin (Sn) Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) -
Terminal pitch 0.3 mm 0.5 mm 0.35 mm 0.5 mm - 0.35 mm 0.5 mm 0.5 mm 0.5 mm
Maximum time at peak reflow temperature NOT SPECIFIED 30 NOT SPECIFIED 30 NOT SPECIFIED NOT SPECIFIED 30 30 -
Base Number Matches 1 1 1 1 - 1 1 1 1
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