A product Line of
Diodes Incorporated
PI6CFGL201B
2-Output Low Power PCIE Gen 1-2-3 Clock Generator
Features
ÎÎ
25MHz crystal or reference clock input
ÎÎ
100MHz low power HCSL or LVDS compatible outputs
ÎÎ
PCIe 3.0, 2.0 and 1.0 compliant
ÎÎ
Selectable spread spectrum of -0.25%, -0.5% and no spread
ÎÎ
Programmable output amplitude and slew rate
ÎÎ
Cycle-to-cycle jitter (typ.) ~ 30ps
ÎÎ
Supply voltage of 3.3V+/-10%
ÎÎ
Output supply voltage of 1.8V (1.05V to 3.6V supported)
ÎÎ
Industrial ambient operating temperature
ÎÎ
Available in lead-free package:
Description
The PI6CFGL201B is a 2-output very low power 100MHz fre-
quency generator for PCIe Gen 1, 2 and 3 applications with inte-
grated output terminations providing Zo=100Ω. The device has
2 output enables for clock management and supports 2 different
spread spectrum levels in addtion to spread off. The device also
has one 1.8V LVCMOS REF1.8 output.
Applications
ÎÎ
PCIe 3.0/2.0/1.0 clock generation
Pin Configuration (24-Pin TQFN)
CKPWRGD_PD#
24-TQFN
GNDXTAL
SS_EN_tri
VDDO1.8
VDDO1.8
XTAL_IN 1
XTAL_OUT 2
VDDXTAL 3
SADR/REF1.8 4
VDDREF1.8 5
GNDDIG 6
24 23 22 21 20 19
OE1#
GND
18 CLK1#
17 CLK1
16 VDDA3.3
15 GNDA
14 CLK0#
13 CLK0
7
VDDDIG3.3
8
SCLK_3.3
9 10 11 12
SDATA_3.3
GND
OE0#
CLK0
CLK0#
CLK1
CLK1#
Block Diagram
XTAL_IN or Ref CLK
XTAL_OUT
OE(1:0)#
I
t
+
OSC
REF1.8
+
SS Capable PLL
u
+
CONTROL
LOGIC
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
PI6CFGL201B
Rev C
17-0082
1
www.diodes.com
June 2017
© Diodes Incorporated
A product Line of
Diodes Incorporated
PI6CFGL201B
SMBus Address Selection Table
SADR
State of SADR on first application of CKPWRGD_PD#
0
1
Address
1101000
1101010
+ Read/Write Bit
1/0
1/0
First rise edge
CKPWRGD_PD#
SADR/REF1.8
Input
Output
Typ. 6us
Power Management Table
CKPWRGD_PD#
0
1
1
SMBus OE bit
x
1
0
Low
Running
Low
CLKx
True O/P
Low
Running
Low
Comp. O/P
REF1.8
Hi-Z
1
Running
Low
Note:
1. REF1.8 is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF1.8 is Low.
CKPWRGD_PD#
0
1
1
1
1
OE (Pin)
X
0
0
1
1
OE (SMBus bit)
x
0
1
0
1
Low
Low
CLKx
True O/P
Low
Low
Running
Low
Low
Comp. O/P
Running
Low
Low
Typical Crystal Requirement
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Min.
Type
Fundamental
25
MHz
Ω
pF
Max.
Units
Recommended Crystal Specification
a) FL2500047, SMD 3.2X2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
Rev C
PI6CFGL201B
17-0082
2
www.diodes.com
June 2017
© Diodes Incorporated
A product Line of
Diodes Incorporated
PI6CFGL201B
Pin Description
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin Name
XTAL_IN
XTAL_OUT
VDDXTAL
SADR/REF1.8
VDDREF1.8
GNDDIG
VDDDIG3.3
SCLK_3.3
SDATA_3.3
GND
VDDO1.8
OE0#
CLK0
CLK0#
GNDA
VDDA3.3
CLK1
CLK1#
OE1#
VDDO1.8
GND
CKPWRGD_
PD#
SS_EN_tri
GNDXTAL
Exposed
Thermal Pad
Type
Input
Output
Power
Input/Output
Power
Power
Power
Input
Input/Output
Power
Power
Input
Output
Output
Power
Power
Output
Output
Input
Power
Power
Input
Description
Crystal input or reference input clock, Nominally 25.00MHz.
Crystal output.
3.3V Power supply for XTAL.
Latch to select SMBus Address/1.8V LVCMOS REF1.8 output. This pin has an internal
pull-down.
Power supply for the REF1.8 output
Ground pin for digital circuitry
3.3V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ground pin.
Power supply, nominal 1.8V, range 1.05V~3.6V.
Active low input for enabling CLK0 pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin for the PLL core.
3.3V power for the PLL core.
Differential true clock output
Differential Complementary clock output
Active low input for enabling CLK1 pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V, range 1.05V~3.6V.
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This
pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
This pin has an internal pull-down.
GND for XTAL
Connect to Ground
23
24
Input
Power
-
PI6CFGL201B
Rev C
17-0082
3
www.diodes.com
June 2017
© Diodes Incorporated
A product Line of
Diodes Incorporated
PI6CFGL201B
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply Voltage to Ground Potential (All VDDx except VDDO)......4.6V
Supply Voltage to Ground Potential (VDDO) .....................................3.6V
All Inputs and Output .....................................................-0.5V toV
DD
+0.5V
Storage Temperature.......................................................... –65°C to +150°C
ESD Protection (Input) ...........................................................2000V(HBM)
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Electrical Characteristics–Current Consumption
(T
A
= -40~85
o
C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)
Symbol
I
DDA
I
DDOP
I
DDTOTAL
I
DDSUSP
I
DDPD
Parameters
Condition
VDDA3.3, PLL Mode, core current consumption
VDDO, output only current consumption. All
outputs active
Total current consumption. All outputs active
@100MHz
Min.
Type
29
6
35
4.5
1.3
Max.
38
8
46
8
1.8
Units
mA
mA
mA
mA
mA
Operating Supply Current
1
Suspend Supply Current
1
Powerdown Current
1,2
VDDxxx, CKPWRGD_PD# = 0, Wake-On-LAN
enabled
CKPWRGD_PD#=0
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Assuming REF1.8 is not running in power down state.
Electrical Characteristics–Differential Output Duty Cycle, Jitter, and Skew
Characterisitics
(T
A
= -40~85
o
C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)
Symbol
t
DC
t
sk
t
jcyc-cyc
Parameters
Duty Cycle
1
Skew, Output to Output
1
Jitter, Cycle to cycle
1
Condition
Measured differentially, PLL Mode
V
T
= 50%
PLL mode
Min.
45
Type
Max.
55
50
50
Units
%
ps
ps
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
PI6CFGL201B
Rev C
17-0082
4
www.diodes.com
June 2017
© Diodes Incorporated
A product Line of
Diodes Incorporated
PI6CFGL201B
Electrical Characteristics–Input/Supply/Common Parameters
(Based on T
A
= -40~85
o
C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)
Symbol
V
DDX
V
DDO
T
A
V
IH
V
IM
V
IL
V
T+
V
T-
V
H
V
OH
V
OL
I
IN
Parameters
Supply Voltage
1
Supply Voltage
1
Ambient Operating
Temperature
1
Input High Voltage
1
Input Mid Voltage
1
Input Low Voltage
1
Schmitt Trigger Postive
Going Threshold Voltage
1
Schmitt Trigger Negative
Going Threshold Voltage
1
Hysteresis Voltage
1
Output High Voltage
1
Outputt Low Voltage
1
Condition
Supply voltage for core, analog
Supply voltage outputs
Min.
3.0
1.05
-40
Type
3.3
1.8
25
Max.
3.6
3.6
85
V
DD
+0.3
0.6 V
DD
0.35 V
DD
0.6 V
DD
0.5 V
DD
0.2 V
DD
Units
V
V
°C
V
V
V
V
V
V
V
Single-ended inputs, except SMBus, SS_EN_tri
SS_EN_tri
Single-ended inputs, except SMBus, SS_EN_tri
Single-ended inputs, except SS_EN_tri
Single-ended inputs, except SS_EN_tri
V
T+
- V
T-
Single-ended outputs, except SMBus. I
OH
=
-2mA
Single-ended outputs, except SMBus. I
OL
=
-2mA
Single-ended inputs, V
IN
= GND, V
IN
= VDD
(exclude XTAL_IN pin)
0.65 V
DD
0.4 V
DD
-0.3
0.5 V
DD
0.4 V
DD
0.05 V
DD
V
DD
-0.45
0.45
-5
5
V
uA
Input Current
1
I
INP
fin
Lpin
C
IN
Cout
t
STAB
f
MODIN
t
LATOE#
t
DRVPD
Input Frequency
1
Pin Inductance
1
Capacitance
1
Clock output Stabiliza-
tion
1, 2
Input SS Modulation
Frequency
1
OE# Latency
1, 3
Tdrive_PD#
1, 3
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down
resistors
XTAL, or XTAL_IN
Control Inputs
Output pin capacitance
From V
DD
Power-Up and after input clock
stabilization or de-assertion of CKPWRGD_
PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
CLK start after OE# assertion
CLK stop after OE# deassertion
CLK output enable after
CKPWRGD_PD# de-assertion
30
1
0.6
-200
200
uA
23
1.5
25
26
7
5
6
1
MHz
nH
pF
pF
ms
31.500
33
3
300
kHz
clocks
us
PI6CFGL201B
Rev C
17-0082
5
www.diodes.com
June 2017
© Diodes Incorporated
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