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8SLVS1118NLGI

Description
FANOUT BUFFER
Categorysemiconductor    Analog mixed-signal IC   
File Size678KB,24 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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8SLVS1118NLGI Overview

FANOUT BUFFER

8SLVS1118NLGI Parametric

Parameter NameAttribute value
typefanout buffer (allocation)
Number of circuits1
Ratio - Input:Output1:18
Differential - Input:OutputYes Yes
enterclock
outputLVDS,LVPECL
Frequency - maximum2GHz
Voltage - Power2.375 V ~ 2.625 V, 3.135 V ~ 3.465 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing48-VFQFN Exposed Pad
Supplier device packaging48-VFQFN(7x7)
1:18, Low Skew, Low Additive Jitter
LVDS/ LVPECL Fanout Buffer
8SLVS1118
Datasheet
Description
The 8SLVS1118 is a high-performance, low-power, differential
1:18 output fanout buffer. This highly versatile device is designed
for the fanout of high-frequency, very low additive phase-noise
clock and data signals. Guaranteed output-to-output and
part-to-part skew characteristics make the 8SLVS1118 ideal for
clock distribution applications that demand well-defined
performance and repeatability.
The device is characterized to operate from a 2.5V or 3.3V power
supply. The integrated bias voltage references enable easy
interfacing AC-coupled signals to the device inputs.
Features
1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer
Low power consumption
Differential PCLK, nPCLK clock pair accepts the following
differential/single-ended input levels: LVDS, LVPECL, and
LVCMOS
Maximum input clock frequency: 2GHz
Propagation delay: 290ps (typical)
Output skew: 40ps (typical)
Low additive phase jitter, RMS: 39fs (typical),
Integration Range: 12kHz – 20MHz,
(f
REF
½
156.25MHz, V
PP
½
1V, V
DD
½
3.3V)
Full 2.5V and 3.3V supply voltage modes
Device current consumption: 180mA (typical) IEE for LVPECL
output mode, 400mA (typical) IDD for LVDS output mode
48-VFQFN, lead-free (RoHS 6) packaging
Transistor count: 1762
-40°C to +85°C ambient operating temperature
Supports case temperature up to 105°C
Block Diagram
8SLV1118I
Q0
nQ0
Q1
nQ1
Q2
nQ2
.
.
.
51k
PCLK
nPCLK
Pull-down
Pull-up /
Pull-down
51k
51k
Q17
nQ17
Voltage
Reference
VREF
SEL_LVDS
Pull-down
51k
©2017 Integrated Device Technology, Inc.
1
July 17, 2017
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