NPIC6C4894-Q100
Power logic 12-bit shift register; open-drain outputs
Rev. 1 — 17 April 2014
Product data sheet
1. General description
The NPIC6C4894-Q100 is a 12-stage serial shift register. It has a storage latch associated
with each stage for strobing data from the serial input (D) to the parallel open-drain
outputs (QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data
in each shift register stage is transferred to the storage register when the latch enable (LE)
input is HIGH. Data in the storage register drives the gate of the output extended-drain
NMOS transistor whenever the output enable input (OE) is HIGH. A LOW on OE causes
the outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the registers. Two serial outputs (QS1 and QS2) are available for
cascading a number of NIC6C4894-Q100 devices. Serial data is available at QS1 on
positive-going clock edges to allow high-speed operation in cascaded systems with a fast
clock rise time. The same serial data is available at QS2 on the next negative going clock
edge. It is used for cascading NPIC6C4894-Q100 devices when the clock has a slow rise
time. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs, provide protection against inductive transients.
This protection makes the device suitable for power driver applications such as relays,
solenoids and other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +125
C
Low R
DSon
12 Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Low power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
HBM AEC-Q100-002 revision D class H2 exceeds 2500 V
CDM AEC-Q100-011 revision C1 class C6 exceeds 1000 V
Nexperia
NPIC6C4894-Q100
Power logic 12-bit shift register; open-drain outputs
3. Applications
LED sign
Graphic status panel
Fault status indicator
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
NPIC6C4894D-Q100
40 C
to +125
C
SO20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
Version
SOT163-1
Type number
NPIC6C4894PW-Q100
40 C
to +125
C
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
5. Functional diagram
Fig 1.
Logic symbol
NPIC6C4894_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 17 April 2014
2 of 21
Nexperia
NPIC6C4894-Q100
Power logic 12-bit shift register; open-drain outputs
Fig 2.
Functional diagram
V
CC
GND
aaa-002550
Fig 3.
Schematic of all inputs
Fig 4.
Schematic of open-drain outputs (QPn)
Fig 5.
Logic diagram
NPIC6C4894_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 17 April 2014
3 of 21
Nexperia
NPIC6C4894-Q100
Power logic 12-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
Fig 6.
Pin configuration SO20 and TSSOP20
6.2 Pin description
Table 2.
Symbol
LE
D
CP
QP0 to QP11
GND
QS1
QS2
OE
V
CC
Pin description
Pin
1
2
3
4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13
10
11
12
19
20
Description
latch enable input
serial data input
clock input
parallel output
ground (0 V)
serial output
serial output
output enable input
supply voltage
NPIC6C4894_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 17 April 2014
4 of 21
Nexperia
NPIC6C4894-Q100
Power logic 12-bit shift register; open-drain outputs
7. Functional description
Table 3.
Function table
[1]
At the positive clock edge, the information in the 10
th
register stage is transferred to the 11
th
register stage and the QS output
Control
CP
[1]
[2]
[3]
Input
OE
L
L
H
H
H
H
LE
X
X
L
H
H
H
D
X
X
X
L
H
H
Parallel output
QP0
Z
Z
no change
Z
L
no change
QPn
Z
Z
no change
QPn1
QPn1
no change
Serial output
QS1
[2]
Q10S
no change
Q10S
Q10S
Q10S
no change
QS2
[3]
no change
Q11S
no change
no change
no change
Q11S
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition;
Z = high-impedance OFF-state.
Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
Fig 7.
Timing diagram
NPIC6C4894_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 17 April 2014
5 of 21
京公网安备 11010802033920号
EEWORLD
