IR3093PbF
DATA SHEET
3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
DESCRIPTION
The IR3093 Control IC provides a full featured, cost effective, single chip solution to implement robust
power conversion solutions for three different microprocessor families; 1) AMD’s Opteron, 2) AMD’s
Athlon or 3) Intel’s VR-10.X family of processors. The user can select the appropriate VID range with a
single pin. Control and 3 phase Gate Drive functions are integrated into a single cost effective IC. . In
addition to CPU power, IR3093 offers a compact, efficient solution for high current POL converters.
FEATURES
x
x
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x
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x
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x
x
5 bit or 6 bit VID with 0.5% overall system accuracy
Selectable VID Code for AMD Opteron or Athlon or Intel VR10.X
Programmable Slew Rate response to “On-the-Fly” VID Code Changes
3A GATELX Pull Down Drive Capability
Programmable 100KHz to 540KHz oscillator
Programmable Voltage Positioning (can be disabled)
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates up to 21V input with 7.9V Under-Voltage Lockout
5V UVL with 4.36V Under-Voltage Lockout threshold
Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
Enable Input
OVP Flag Output detects high side fet short at powerup
Pin compatible with IR3092, 2-phase PWM Control IC
Available 48L MLPQ package
ORDERING INFORMATION
Device
IR3093MTRPbF
IR3093MPbF
Order Quantity
3000 per Reel
100 piece strips
PACKAGE INFORMATION
VID2
VID1
VID0
VID5
5VREF
OVPSNS
ENABLE
OVP
CSINP1
CSINM1
NC
VCCH1
Page 1 of 39
LGND
SETBIAS
VCC
CSINP3
CSINM3
BIASOUT
PWRGD
CSINP2
CSINM2
VID_SEL
VCCL3
GATEL3
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
IR3093
48LD MLPQ
GATEH1
PGND1
GATEL1
VCCL1_2
5VUVL
GATEL2
PGND2
GATEH2
VCCH2
VCCH3
GATEH3
PGND3
48L MLPQ
(7 x 7 mm Body)
o
JA
= 27 C/W
09/08/05
IR3093PbF
PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PIN SYMBOL
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
LGND
SETBIAS
VCC
CSINP3
CSINM3
BIASOUT
PWRGD
CSINP2
CSINM2
VID_SEL
VCCL3
GATEL3
PGND3
GATEH3
VCCH3
VCCH2
GATEH2
PGND2
GATEL2
5VUVL
VCCL1_2
GATEL1
PGND1
GATEH1
VCCH1
NC
CSINM1
CSINP1
OVP
ENABLE
OVPSNS
5VREF
VID5
VID0
VID1
VID2
PIN DESCRIPTION
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents
Remote Sense Input. Connect to ground at the Load.
Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current
source.
Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced
to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.
Buffered IIN signal. Connect an external RC network to FB to program converter output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an
external resistor connected to the converter output voltage at the load and an internal current source. Bias
current is a function of ROSC. Also OVP sense
Output of the Error Amplifier
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to
program the timing.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 is forced to match phase 1’s current.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 3 is forced to match phase 1’s current.
Local Ground and IC substrate connection
External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
Power for internal circuitry and source for BIASOUT regulator
Non-inverting input to the Phase 3 Current Sense Amplifier.
Inverting input to the Phase 3 Current Sense Amplifier.
200mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
Non-inverting input to the Phase 2 Current Sense Amplifier.
Inverting input to the Phase 2 Current Sense Amplifier.
Ground Selects VR10.X VID, Float Selects OPTERON VID, VCC Selects ATHLON VID
Power for Phase 3 Low-Side Gate Driver.
Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator.
Return for Phase 3 Gate Drivers
Phase 3 High-Side Gate Driver Output and input to GATEL3 non-overlap comparator.
Power for Phase 3 High-Side Gate Driver
Power for Phase 2 High-Side Gate Driver
Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
Return for Phase 2 Gate Drivers
Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
Power for Phase 1 and 2 Low-Side Gate Drivers.
Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
Return for Phase 1 Gate Drivers
Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
Power for Phase 1 High-Side Gate Driver
Not connected
Inverting input to the Phase 1Current Sense Amplifier.
Non-inverting input to the Current Sense Amplifier.
Output that drives high during an Over-Voltage condition.
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
Dedicated output voltage sense pin for Over Voltage Protection.
Compensation for internal voltage reference rail.
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Page 2 of 39
09/08/05
IR3093PbF
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 7.4V
V
CC
21V, 4V
V
CCLX
14V,
o
o
4V
V
CCHX
28V, C
GATEHX
=3.3nF, C
GATELX
=6.8nF, 0 C
T
J
125 C
TEST CONDITION
-0.3V
VOSNS-
0.3V, Connect FB to
EAOUT, Measure V(EAOUT) –
V(VOSNS-) deviation from Table 1.
Applies to all VID codes.
R
ROSC
= 47k
9'$& 2&6(7
R
ROSC
= 47k
9'$& 2&6(7
VID_SEL=0, Referenced to VOSNS-
VID_SEL=Float, Referenced to VOSNS-
MIN
TYP
MAX
UNIT
PARAMETER
VDAC Reference
System Set-Point Accuracy
Sink Current
Source Current
VID Input Threshold, INTEL
VID Input Threshold, AMD
VID_SEL OPTERON
Threshold
VID_SEL ATHLON Threshold
VID_SEL Float Voltage
VID_SEL Pull-up Resistance
VID_SEL Pull-down
Resistance
VID Pull-up Current
VID Float Voltage
VID = 11111 Fault Blanking
Error Amplifier
Input Offset Voltage
FB Bias Current
DC Gain
Gain-Bandwidth Product
Slew Rate
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP Buffer Amplifier
Positioning Offset Voltage
Output Voltage Range
0.5
45
48
0.4
1.55
1.0
53
56
0.6
1.65
1.2
3.3
2.6
50
150
18
4.9
2.1
61
64
0.8
1.75
1.4
3.8
3.2
100
350
27
5.2
4.1
%
PA
V
V
V
V
V
k
k
PA
V
Ps
Tracks ATHLON threshold
V(VID_SEL)<2.1V
V(VID_SEL)>3.2V
VID0-5 = 1V
Referenced to LGND
Delay to PWRGD assertion
Connect FB to EAOUT, Measure
V(EAOUT)-V(VDAC). Applies to all VID
codes and -0.3V<VOSNS-<0.3V. Note
2.
R
ROSC
= 47k
Note 1
Note 1
Note 1, 50mV FB signal
3.0
2.1
30
60
9
4.5
0.5
-5
23.5
90
4
300
.75
4.5
-1
26.4
100
7
1.25
430
1.1
4.9
50
0
3
29.4
105
mV
PA
dB
MHz
V/Ps
PA
mA
V
mV
mV
V
600
1.5
5.3
200
125
3.75
V(VDRP) – V(VDAC) with
CSINMX=CSINPX=0. Note 1.
-125
0.2
Page 4 of 39
09/08/05
IR3093PbF
PARAMETER
VDRP Buffer Amplifier cont.
Source Current
Sink Current
Oscillator
Switching Frequency
Phase Shift
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
BIASOUT Dropout Voltage
BIASOUT Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Hiccup Discharge Current
OC Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
Max OCSET Set Point
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
TEST CONDITION
MIN
4
200
R
ROSC
= 47k
Sequence: GATEH1-GATEH2-GATEH3
R
ROSC
= 47k
V(SETBIAS)-V(BIASOUT) @ 100mA
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
160
102
94
0.1
1.2
150
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
0.8
30
3.5
25
9
3.8
190
170
TYP
8
300
200
120
103
0.25
1.8
250
1.1
60
6
55
10
4.0
250
265
MAX
20
650
240
138
117.5
0.55
2.5
450
1.8
90
9
70
13
4.2
300
350
UNIT
mA
PA
kHz
°
PA
V
V
mA
V
PA
PA
PA
PA/PA
V
mV
mV
Relative to Charge Voltage
V(OCSET)-V(VDAC),
CSINM=CSINP1=CSINP2=CSINP3,
Note 1.
R
ROSC
= 47k
-125
23.5
3.9
7.4
6.9
400
4.05
3.92
100
0
27
125
29.4
mV
PA
V
V
V
mV
V
V
mV
Start – Stop
Start – Stop
7.9
7.4
540
4.36
4.17
200
8.4
7.9
700
4.55
4.33
250
Page 5 of 39
09/08/05
DSP and ARM Processors
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