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SI4122-D-GM

Description
IC SYNTH RF2/IF SNGL-BAND 28MLP
CategoryAnalog mixed-signal IC    The signal circuit   
File Size947KB,36 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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SI4122-D-GM Overview

IC SYNTH RF2/IF SNGL-BAND 28MLP

SI4122-D-GM Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeQFN
package instructionHVQCCN,
Contacts28
Reach Compliance Codecompliant
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeS-XQCC-N28
length5 mm
Number of functions1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height0.9 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width5 mm
Si4133
Si4123/22/13/12
D
U A L
- B
A N D
R F S
Y N T H E S I Z E R
W
I T H
I
N TE G R A T E D
V C O
S
F
OR
W
I R E L E S S
C
O M M U N I C A T I O N S
F
EATURES
Dual-band RF synthesizers
900 MHz to 1.8 GHz

RF2: 750 MHz to 1.5 GHz

RF1:
IF synthesizer

IF:
62.5 to 1000 MHz
Integrated VCOs, loop filters,
varactors, and resonators
Minimal (2) number of external
components required
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP,
28-lead QFN

Lead-free
Ordering Information:
See page 31.
and RoHS compliant
Applications
Pin Assignments
Dual-band communications
Digital cellular telephones GSM 850, E-GSM 900, DCS 1800,
PCS 1900
Digital cordless phones
Analog cordless phones
Wireless local loop
Si4133-GT
SCLK
SDATA
GNDR
RFLD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
Description
The Si4133 is a monolithic integrated circuit that performs both IF and dual-
band RF synthesis for wireless communications applications. The Si4133
includes three VCOs, loop filters, reference and VCO dividers, and phase
detectors. Divider and powerdown settings are programmable with a three-
wire serial interface.
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
Functional Block Diagram
VDDR
XIN
SDATA
IFOUT
GNDR
Reference
Amplifier
Powerdown
Control
R
Si4133-GM
SCLK
RF1
PWDN
N
R
Phase
Detector
RF2
RFOUT
GNDR
28 27 26 25 24 23 22
1
2
3
4
5
6
7
8
GNDR
SEN
VDDI
RFLB
GNDI
Phase
Detector
RFLA
21
20
19
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
SDATA
SCLK
SEN
Serial
Interface
22-bit
Data
Register
RFLC
RFLD
RFLD
RFLC
GNDR
RFLB
N
R
Phase
Detector
IF
GND
Pad
18
17
16
15
AUXOUT
Test
Mux
IFDIV
IFOUT
RFLA
GNDR
PWDN
GNDR
Patents pending
Rev. 1.61 1/10
Copyright © 2010 by Silicon Laboratories
Si4133
RFOUT
GNDD
VDDR
IFLB
AUXOUT
N
IFLA
9
10 11 12 13 14

SI4122-D-GM Related Products

SI4122-D-GM SI4113-D-GMR SI4122-D-GMR SI4113-D-GT SI4112-D-GTR SI4123-D-GT SI4133-D-GMR SI4122-D-GT
Description IC SYNTH RF2/IF SNGL-BAND 28MLP IC SYNTHESIZER RF-ONLY 28MLP IC SYNTH RF2/IF SNGL-BAND 28MLP IC SYNTHESIZER RF1/RF2 24TSSOP IC SYNTHESIZER IF ONLY 24TSSOP IC SYNTHESIZER RF1/IF 24TSSOP IC SYNTHESIZER RF DUALBAND 28MLP IC SYNTHESIZER RF2/IF 24TSSOP
Is it lead-free? Lead free Lead free Lead free Lead free Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to
Maker Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc
Parts packaging code QFN QFN QFN TSSOP TSSOP TSSOP QFN TSSOP
package instruction HVQCCN, HVQCCN, HVQCCN, TSSOP, TSSOP, TSSOP, HVQCCN, TSSOP,
Contacts 28 28 28 24 24 24 28 24
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
Analog Integrated Circuits - Other Types PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP PHASE LOCKED LOOP
JESD-30 code S-XQCC-N28 S-XQCC-N28 S-XQCC-N28 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 S-XQCC-N28 R-PDSO-G24
length 5 mm 5 mm 5 mm 7.8 mm 7.8 mm 7.8 mm 5 mm 7.8 mm
Number of functions 1 1 1 1 1 1 1 1
Number of terminals 28 28 28 24 24 24 28 24
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY UNSPECIFIED PLASTIC/EPOXY
encapsulated code HVQCCN HVQCCN HVQCCN TSSOP TSSOP TSSOP HVQCCN TSSOP
Package shape SQUARE SQUARE SQUARE RECTANGULAR RECTANGULAR RECTANGULAR SQUARE RECTANGULAR
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260 260 260 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 0.9 mm 0.9 mm 0.9 mm 1.2 mm 1.2 mm 1.2 mm 0.9 mm 1.2 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Nominal supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
surface mount YES YES YES YES YES YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form NO LEAD NO LEAD NO LEAD GULL WING GULL WING GULL WING NO LEAD GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.65 mm 0.65 mm 0.65 mm 0.5 mm 0.65 mm
Terminal location QUAD QUAD QUAD DUAL DUAL DUAL QUAD DUAL
Maximum time at peak reflow temperature 40 40 40 40 40 40 40 40
width 5 mm 5 mm 5 mm 4.4 mm 4.4 mm 4.4 mm 5 mm 4.4 mm
JESD-609 code - e3 e3 - e3 e4 e3 e4
Terminal surface - Matte Tin (Sn) Matte Tin (Sn) - Matte Tin (Sn) Silver (Ag) Matte Tin (Sn) Silver (Ag)
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