ZL40260LDG1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> ZL40260LDG1

ZL40260LDG1: DescriptionLOW SKEW, LOW ADDITIVE JITTER 2; Categorylogic logic; File Size777KB，21 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric Compare View All

ZL40260LDG1 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ZL40260LDG1	-	-	View	Buy Now

ZL40260LDG1 Overview

LOW SKEW, LOW ADDITIVE JITTER 2

ZL40260LDG1 Parametric

Parameter Name	Attribute value
Maker	Microsemi
package instruction	HVQCCN, LCC32,.2SQ,20
Reach Compliance Code	compliant
Other features	ALSO OPERATES AT 3.3 V SUPPLY
series	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32
length	5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TRAY
Maximum supply current (ICC)	185 mA
propagation delay (tpd)	1.186 ns
Same Edge Skew-Max（tskwd）	0.05 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	5 mm
minfmax	1600 MHz
Base Number Matches	1

Preview

Download Datasheet

View All

Data Sheet

ZL40260

Low Skew, Low Additive Jitter 2 x10 LVPECL Fanout Buffer

Features



Two inputs accept any differential (LVPECL, HCSL,

LVDS, SSTL, CML) or single ended LVCMOS signal



Ten 2.5V/3.3V LVPECL outputs



Ultra-low additive jitter: 53fs for 125 MHz clock

measured in 12KHz to 20MHz band



Supports clock frequencies from 0 to 1.6GHz



Supports 2.5V or 3.3V power supplies



Embedded Low Drop Out (LDO) Voltage regulator

provides superior Power Supply Noise Rejection



Maximum output to output skew of 50ps



Maximum input to output delay of 1.2ns



Small input to output delay variation over voltage,

temperature and process of 0.34ns



Fast rise and fall times of 168ps



Phase noise floor below -160dB/Hz for 125MHz

clock



ZL40260LDG1

ZL40260LDF1

ZL40260QGG1

ZL40260QGF1

Ordering Information

32 Pin QFN

32 pin QFN

32 pin eTQFP

Trays

Tape and Reel

Trays

Tape and Reel

Package size: 5 x 5 mm QFN and 7 x 7 mm eTQFP

-40



C to +85



-40



C to +85



Applications

General purpose clock distribution

Low jitter clock trees

Logic translation

Clock and data signal restoration

Wired communications: OTN, SONET/SDH, GE, 10 GE,

FC and 10G FC

PCI Express generation 1/2/3/4 clock distribution

Wireless communications

High performance microprocessor clock distribution

Test equipment

ZL40260

OUT0_p

OUT0_n

OUT1_p

OUT1_n

CLK_SEL

OUT2_p

OUT2_n

IN0_p

IN0_n

OUT3_p

OUT3_n

IN1_p

IN1_n

OUT4_p

OUT4_n

OUT5_p

OUT5_n

Vbb

OUT6_p

OUT6_n

OUT7_p

OUT7_n

OUT8_p

OUT8_n

OUT9_p

OUT9_n

Figure 1. Functional Block Diagram

ZL40260

September 2017

Data Sheet

ZL40260

Table of Contents

Features ............................................................................................................................... 1

Applications .......................................................................................................................... 1

Table of Contents.................................................................................................................. 2

Pin Diagram .......................................................................................................................... 5

Pin Descriptions .................................................................................................................... 6

Functional Description........................................................................................................... 8

Clock Inputs .......................................................................................................................... 8

Clock Outputs ..................................................................................................................... 11

Termination of unused inputs and outputs ........................................................................... 13

Power Consumption............................................................................................................ 13

Power Supply Filtering ........................................................................................................ 13

Power Supplies and Power-up Sequence............................................................................ 13

AC and DC Electrical Characteristics .................................................................................. 13

Absolute Maximum Ratings................................................................................................. 14

Recommended Operating Conditions .................................................................................. 14

DC Electrical Characteristics ............................................................................................... 15

QFN and eTQFP Package Outline ...................................................................................... 19

September 2017

ZL40260

Data Sheet

ZL40260

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Functional Block Diagram ........................................................................................................................................... 1

Pin Diagram (not to scale) .......................................................................................................................................... 5

Input driven by a AC coupled LVPECL output .............................................................................................................. 8

Input driven by a DC coupled LVPEVCL output............................................................................................................ 8

Input driven by AC coupled LVDS output .................................................................................................................... 9

Input driven by 3.3V CML output ................................................................................................................................ 9

Input driven by 3.3V CML output with internal pull-ups ............................................................................................. 9

Input driven by SSTL output ...................................................................................................................................... 10

Input driven by single-ended output ......................................................................................................................... 10

Termination for 3.3V LVPECL outputs ....................................................................................................................... 11

Alternative termination for 3.3V LVPECL outputs ..................................................................................................... 11

Termination for 2.5V LVPECL output ........................................................................................................................ 11

Alternative termination for 2.5V LVPECL output ...................................................................................................... 12

September 2017

ZL40260

ZL40260LDG1 Related Products

	ZL40260LDG1	ZL40260LDF1
Description	LOW SKEW, LOW ADDITIVE JITTER 2	LOW SKEW, LOW ADDITIVE JITTER 2

Recommended Resources

CMOS interface circuit

A circuit diagram for channel monitoring using AD5380 multi-channel DAC

Voice controlled delay light switch circuit (3)

Punched Tape Reading Circuit

Graphical interface circuit

845ddr computer motherboard circuit diagram_20

Ask about the configuration of multiple FPGAs: I connected three FPGAs in a daisy chain and configured them in serial loading mode . Question: The first FPGA mode is M0=0, M1=0, M2=1; the last FPGA mode can be set to M0=1, M1=1, M2=1. So, what mod...; eeleader FPGA/CPLD

Zhou Ligong S3C2410 BSP sleep button problem: I transplanted Zhou Ligong 2410 WINCE5.0 BSP to my own board. When I use IRQ_EINT0 as interrupt in PWRBUTTON, there is no response. But when I use IRQ_EINT1 as interrupt, I can enter sleep mode. I tho...; 123amy Embedded System

Five successful cases of RFID application and their analysis: Five successful cases of RFID application and their analysis...; chenjianeng RF/Wirelessly

Electronic smart products account for nearly 1/4 of the total vehicle value and are increasing year by year: With the continuous improvement of the level of electronic intelligent technology, countries with developed automobile industries in the world have begun to apply automotive electronic intelligent tec...; frozenviolet Automotive Electronics

Show the process of WEBENCH design + design low-pass filter: The first step, select the filter page designThe second step, the system filters the results, and selects the appropriate structural model designThe third step, select the first 6db structural model l...; youzizhile Analogue and Mixed Signal

【Video download】Learn msp430 video tutorial in ten days: [i=s] This post was last edited by paulhyde on 2014-9-15 03:09 [/i] Part 1 Hardware Structure Lecture 1 Overview 54 minutes Lecture 2 Reset, Interrupt and IO 70 minutes Lecture 3 Asynchronous Communic...; open82977352 Electronics Design Contest

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components