NB3H5150
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150 is a high performance Multi−Rate Clock generator
which simultaneously synthesizes up to four different frequencies
from a single PLL using a 25 MHz input reference. The reference
frequency can be provided by a crystal, LVCMOS/LVTTL, LVPECL,
HCSL or LVDS differential signals. The REFMODE pin will select
the reference source.
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 25 MHz, 33.33 MHz, 50 MHz,
100 MHz, 125 MHz, or 156.25 MHz and have ultra−low noise/jitter
performance of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
following integer and FRAC−N frequencies in pin−strap mode:
33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz,
133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I
2
C and SMBUS) interface can be used to load register
files into the NB3H5150 to program a variety of functions including
the frequencies and output levels of each output which can be
individually enabled and disabled.
Features
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MARKING
DIAGRAM*
1
1
32
A
WL
YY
WW
G
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
•
Flexible Input Reference − 25 MHz Crystal, Oscillator,
•
•
Single−Ended or Differential Clock
Four Independent User−Programmable Clock
Frequencies from 25 MHz to 250 MHz
Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V
±5%
or 2.5 V
±5%
VDDO
n
(Outputs) = 3.3 V
±5%
or 2.5 V
±5%
or
1.8 V
±5%
(LVCMOS Only)
Independent Power Supply for each Output Bank
300 ps max Output Rise and Fall Times, LVPECL
1000 ps max Output Rise and Fall Times, LVCMOS
300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
•
1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
•
•
•
•
•
•
•
•
•
•
•
155.52 MHz
I
2
C / SMBus Compatible Interface
−40°C to +85°C Ambient Operating Temperature
Zero ppm Multiplication Error
Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
32−Pin QFN, 5 mm x 5 mm
This is a Pb−Free Device
•
•
•
•
•
Applications
Telecom
Networking
Ethernet
SONET
©
Semiconductor Components Industries, LLC, 2016
1
March, 2016 − Rev. 3
Publication Order Number:
NB3H5150/D
NB3H5150
VDD AVDD1
AVDD2
AVDD3
REF (I2C Mode)
CLK_XTAL1
CLK_XTAL2
XTAL
OSC
PLL
VDDO1
Integer N
DIV1
CLK1A
CLK1B
VDDO2
Integer N
DIV2
CLK2A
CLK2B
VDDO3
Integer N
DIV3
CLK3A
CLK3B
VDDO4
LDOs
Integer N or
Fractional N
DIV4
CLK4A
CLK4B
SDA
SCL/PD
MMC
REFMODE
FTM
Configuration Table
&
I2C Interface
LDO1 LDO2 LDO3 LDO4
FS4A
CLK_XTAL1
Figure 1. Simplified Block Diagram of NB3H5150
FS4B
FS1
FS2
FS3
LDO1
VDDO1
25
AVDD1
AVDD2
CLK1A
CLK1B
LDO2
Exposed Pad (EP)
32
CLK_XTAL2
REFMODE
SDA
SCL/PD
VDD
FS1
FS2
FS3
1
2
3
4
5
6
7
8
9
FS4A
31
30
29
28
27
26
24
23
22
21
FTM
CLK2B
CLK2A
VDDO2
VDDO3
CLK3A
CLK3B
MMC
NB3H5150
20
19
18
17
10
FS4B
11
LDO4
12
AVDD3
13
LDO3
14
CLK4A
15
CLK4B
16
VDDO4
Figure 2. 32−Lead QFN Pinout
(Top View)
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2
NB3H5150
Table 1. PIN DESCRIPTION
Pin
1
Name
CLK_XTAL2
I/O
Crystal or
LVPECL/LVDS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power
Power
Power
Output
Output
Power
LVTTL/LVCMOS
Input
Output
Output
Power
Power
Output
Output
Description
Crystal Output or Differential Clock Input (complementary); If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
Reference Input Select to either use a crystal, or overdrive with a single−ended or
differential input; see Table 2. Internal pull−down.
Serial Data Input for I2C/SMBus compatible; Defaults High when left open; internal pull−up.
5V tolerant.
Serial Clock Input for I2C/SMBus compatible; Defaults High when left open; internal
pull−up.
SCL/PD is also a device power−down pin (when High) in pin−strap mode only. 5V tolerant.
3.3 V / 2.5 V Positive Supply Voltage for the Inputs and Core
Frequency Select 1 for DIV1, CLK1A & CLK1B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 2 for DIV2, CLK2A & CLK2B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 3 for DIV3, CLK3A, & CLK3B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 4A for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
Frequency Select 4B for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD3 = VDD.
1.8V LDO − Install Power Conditioning Bypass Capacitor to Ground
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 4
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 4 Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK4A/4B Outputs
Mix Mode Control Pin for use as a combination of FSn settings and I2C setting for the
CLK(n) outputs in the I2C mode; see Table 6. No logic level default; use a RPull−up resistor
for High or a RPull−down resistor for Low.
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 3 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 3
Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK3A/3B Outputs
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK2A/2B Outputs
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 2
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 2 Output
Factory Test Mode. Must connect this pin to Ground.
Power
Output
Output
Power
Power
Power
Power
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK1A/1B Outputs
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 1 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 1
Output
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD2 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD1 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
2
3
4
REFMODE
SDA
SCL/PD
5
6
7
8
9
10
11
12
13
14
15
16
17
VDD
FS1
FS2
FS3
FS4A
FS4B
LDO4
AVDD3
LDO3
CLK4A
CLK4B
VDDO4
MMC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CLK3B
CLK3A
VDDO3
VDDO2
CLK2A
CLK2B
FTM
VDDO1
CLK1B
CLK1A
AVDD2
LDO2
AVDD1
LDO1
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NB3H5150
Table 1. PIN DESCRIPTION
Pin
32
Name
CLK_XTAL1
I/O
Crystal or
LVTTL/LVCMOS
or LVPECL/LVDS
Input
Ground
Description
Crystal Input or Single−Ended or Differential Clock Input; If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
EP
Exposed Pad
Ground – Negative Power Supply is connected via the Exposed Pad .
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is electrically connected to the die,carries all power supply return
currents and must be electrically connected to GND.
1. All VDD, AVDDn, VDDOn, EP (GND) pins must be externally connected to a power supply for proper operation. VDD and AVDDn must all
be at the same voltage.
NB3H5150 BASIC OPERATION
Introduction
The NB3H5150 is a Multi−Rate Clock Generator. The
clock reference for the PLL can be either a 25 MHz crystal,
single−ended LVCMOS or LVTTL signal or a differential
LVPECL, LVDS or HCSL signal.
There are two modes of operation for the NB3H5150,
Pin−Strap and I
2
C.
In the
Pin−Strap Mode,
the user can select any of the
defined output frequencies for each of the four output banks
as specified in Tables 3 and 4 via the three−level Frequency
Select pins: FS1, FS2, FS3, FS4A and FS4B.
In the
I
2
C mode,
the user can select one of the approved
register files in Table 5. Each register file is an expanded
selection of output frequencies and level combinations,
output enable/disable and bypass mode functions.
CLKnA & CLKnB − Output Frequency and Output
Level Selection
The I
2
C interface pins, SCL and SDA, are used to load
register files into the NB3H5150.
These register files will configure the internal registers to
achieve an expanded selection of output frequencies and
levels combinations for each of the four output blocks.
Subsequent changes in the registers can then be performed
with another register file to modify any of the output
frequencies or output modes.
OE, Output Enable
An OE, Output Enable/Disable function is available only
in the I
2
C mode by loading a register file, such that any
individual output bank can be enabled or disabled. In
LVCMOS modes outputs will disable LOW for CLKnA and
CLKnB, while the LVPECL mode outputs will disable
CLKnA = Low and CLKnB = High.
Mixed Mode Control (MMC)
There are four output banks: CLK1A&B, CLK2A&B and
CLK3A&B are integer only divider outputs, whereas
CLK4A&B can be set or programmed as an integer or
fractional divider.
The output levels for each output bank can be LVPECL
(differential) or LVCMOS (two single−ended). Output
Enable / Disable functions are available in I
2
C only.
CLK1, 2, 3 and 4 outputs are not phase−aligned, in PLL
or PLL bypass modes.
Power−On Output Default
In the I
2
C mode, the Mixed Mode Control (MMC) pin is
used for a combination of FSn settings and I
2
C settings to
control the CLK(n) outputs’ function as defined in Table 7.
REFMODE – Select a Crystal or External Clock Input
Interface
(See Table 2)
Upon power−up, all four outputs will be forced to and held
at static LVPECL levels (CLKnA = Low, CLKnB = High)
until the PLL is stable. The PLL will be stable before any of
the output Clocks, CLKnx, are enabled.
SDA & SCL/PD - Serial Data Interface – I2C
The REFMODE pin will select the reference input for the
CLK_XTAL1 and CLK_XTAL2 pins to use either a crystal,
an overdriven single−ended or differential input.
When using a crystal, set the REFMODE pin to a LOW.
The CLK_XTAL1 and CLK_XTAL2 input pins will accept
a 25 MHz crystal.
When using a direct−coupled differential input, set the
REFMODE pin to a HIGH.
The NB3H5150 incorporates a two−wire Serial Data
Interface to expand the flexibility and function of the
NB3H5150 clock generator.
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4
NB3H5150
When REFMODE is HIGH, the CLK_XTAL1 and
CLK_XTAL2 differential input pins have internal AC
coupling capacitors selected with self−bias circuity for the
differential input buffer. This differential buffer will directly
accept any differential signal including LVPECL, LVDS,
HCSL or CML. Drive the CLK_XTAL1 pin with the true
signal and the CLK_XTAL2 pin with the complementary
signal.
When overdriving the CLK_XTAL1 input pin with a
single−ended signal set REFMODE to a HIGH, and connect
CLK_XTAL2 to Ground. The input has internal AC
coupling capacitor with self−bias circuitry.
Table 2. CRYSTAL INPUT INTERFACE AND REFMODE TRUTH TABLE
Input Mode Crystal/External Clock
Crystal
Any Differential Input
Single−Ended Input
REFMODE
LOW
HIGH
HIGH
CLK_XTAL1
Use a Crystal
Overdrive with True Input
Overdrive
CLKb_XTAL2
Use a Crystal
Overdrive with Complementary Input
Connect to Ground
LVCMOS Outputs
EP Exposed Pad
LVCMOS outputs are powered with VDDOn = 3.3 V,
2.5 V or 1.8 V
A 33
W
series terminating resistor may be used on each
clock output if the metal trace is longer than one inch.
Any unused LVCMOS output can be left floating, but
there should be no metal trace attached to the package pin.
LVPECL Differential Outputs
The exposed pad on the bottom side of the package must
be connected to Ground.
LDO Pins
The differential LVPECL outputs are powered with
VDDO = 3.3 V or 2.5 V and must be properly loaded. See
Figure 10.
Any unused differential output pair should either be left
floating or terminated.
REF Out
The NB3H5150 has integrated low noise 1.8 V
Low−Drop−Out (LDO) voltage regulators which provide
power internal to the NB3H5150.
The LDOs require decoupling capacitors in the range of
1
mF
to 10
mF
for compensation and high frequency PSR.
When powered−down, the device turns off the LDOs and
enters a low power shutdown mode consuming less than
1 mA.
FTM
In the PLL bypass mode available via
the input
reference frequency can be routed to CLK1A and CLK1B as
phase aligned LVCMOS or differential LVPECL outputs
with the same frequency. The output frequency and duty
cycle equals the input frequency and duty cycle.
Power Supplies
I
2
C,
This is a Factory Test Mode pin and must be connected to
the Ground of the application for proper operation.
PIN−STRAP / FSn Frequency Select MODE: (see
Tables 3 and 4)
The NB3H5150 has several power supply pins:
•
VDD is the supply voltage for the input and digital core
circuitry.
•
AVDD1, AVDD2 and AVDD3 powers the core analog
circuits. VDD = AVDD1 = AVDD2 = AVDD3.
•
VDDO1, VDDO2, VDDO3 and VDDO4 are individual
power supplies for each of the four CLKnA/B output
banks.
Upon power−up, all four VDDOn pins must be connected
to a power supply, even if only one output is being used.
Any combination of VDD and VDDOn power supply
voltages is allowed.
A power supply filtering scheme in Figure 8 is
recommended for best device performance.
When all VDD, AVDDn and VDDOn pins reach their
minimum voltage per Table 10, the NB3H5150 will operate
at the proper output frequencies.
The NB3H5150 can be configured to operate in pin−strap
mode where the control pins FSnA/B can be set to generate
the necessary clock outputs of the device.
Prerequisites:
♦
SDA and SCL/PD must be Low at all times while in
pin−strap mode to enable FS control. If SDA ever
goes High, pin−strap is exited and the only way to
go back is to power cycle the device.
♦
Mixed Mode Control pin (MMC) level will be
IGNORED.
Sequencing:
1. Upon device power−up (assuming SCL is LOW)
a. All four CLK(n) frequency and output type
selections will be pre−loaded according to the
FS pin settings, but all four outputs will be held
at static LVPECL levels (CLKnA = Low,
CLKnB = High) until the PLL has become
stable.
b. After the PLL is stable, all CLK(n) output type
selections (i.e. LVPECL or LVCMOS) will
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