The SY89429A is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a range
of frequencies from 400MHz to 800MHz. The differential PECL
output can be configured to be the VCO frequency divided by
2, 4, 8 or 16. With the output configured to divide the VCO
frequency by 2, and with a 16MHz external quartz crystal used
to provide the reference frequency, the output frequency can
be specified in 1MHz steps.
n
Internal quartz reference oscillator driven by quartz
crystal or PECL source
n
PECL output can operate with either +3.3V or +5V
VCC_OUT power supply
n
External loop filter optimizes performance/cost
n
Applications note (AN-06) for ease of design-ins
n
Available in PLCC and SOIC 28-pin packages
PIN CONFIGURATION
FOUT
/FOUT
GND
VCC (TTL)
GND (TTL)
VCC_OUT
TEST
M[0] 1
M[1] 2
18
17
28 /P_LOAD
27 VCC1
26 XTAL2
25 XTAL1
24 LOOP_REF
23 LOOP_FILTER
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
VCC_QUIET
LOOP_FILTER
LOOP_REF
XTAL1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
PLCC
TOP VIEW
16
15
14
13
12
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
M[2] 3
M[3] 4
M[4] 5
M[5] 6
M[6] 7
M[7] 8
M[8] 9
N[0] 10
N[1] 11
GND (TTL) 12
TEST 13
SOIC
TOP VIEW
22 VCC_QUIET
21 S_LOAD
20 S_DATA
19 S_CLOCK
18 VCC_OUT
17 FOUT
16 /FOUT
15 GND
VCC1
/P_LOAD
M[0]
M[1]
M[2]
APPLICATIONS
n
n
n
n
n
n
n
n
Workstations
Advanced communications
High end consumer
High-performance computing
RISC CPU clock
Graphics pixel clock
Test equipment
Other high-performance processor-based
applications
XTAL2
M[3]
VCC (TTL) 14
Precision Edge is a registered trademark of Micrel, Inc.
1
Rev.: K
Amendment: /0
Issue Date: July 2009
Micrel, Inc.
Precision Edge
®
SY89429A
BLOCK DIAGRAM
+5.0V
PLL
÷8
FREF
PHASE DETECTOR
V CO
10-25MHz
Fundamental
Crystal
or
PECL
Source
PECL
OSC
÷M
400 – 800
MHz
÷N
FOUT
3 WIRE
INTERFACE
SERIAL
PARALLEL
INTERFACE
LOGIC
TEST
CONFIG. INFO
DETAILED BLOCK DIAGRAM
+5.0V
2
LOOP
_FILT ER
F RE F
3
LOOP
_RE F
1
V
C C_QUIE T
+5.0V
6, 21
V
C C1
÷8
P HASE DET EC TOR
V CO
400-800
MHz
T 110
÷N
(2,4,8,16)
V
C C_OUT
+5.0V
25
24
23
F OUT
F OUT
10–25MHz
F undamental
C rystal
or
P EC L
S ource
4
XTAL1
OSC
XTAL2
L = LAT CH
H = T rans parent
1
0
5
9-B IT ÷ M
C OUNT ER
S _
LOAD
P _
LOAD
28
7
LAT CH
LAT CH
F OUT ÷ 4 — 7
S _
C LOCK
÷ M — 6
LAT CH
0
1
0
1
LOW — 5
F OUT — 4
÷M— 3
F RE F — 2
20
T ES T
S _
DAT A
S _
C LOCK
27
26
HIG H — 1
9-B IT S R
2-B IT S R
3-B IT S R
0
8 -> 16
9
M[8:0]
17,18
2
N[1:0]
19,22
NOTE:
Pin numbers reference PLCC pinout.
2
Micrel, Inc.
Precision Edge
®
SY89429A
PIN DESCRIPTIONS
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. Alternatively, these pins
can be driven with 100K PECL level by an external source.
S_
LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_
LOAD
for proper operation.
S_
DATA
This TTL pin is the input to the serial configuration shift
registers.
S_
CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_
DATA
is sampled.
P_
LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when
this signal is LOW; thus, the parallel data must be stable on
the LOW-to-HIGH transition of P_
LOAD
for proper operation.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of P_
LOAD
.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of P_
LOAD
.
OUTPUTS
FOUT, FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
V
CC1
This is the positive supply for the chip and is normally connected
to +5.0V.
V
CC_OUT
This is the positive reference for the PECL outputs, FOUT and
FOUT. It is constrained to be less than or equal to
VCC1
.
V
CC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage
for the PLL.
N[1:0]
00
01
10
11
Output Division
2
4
8
16
3
Micrel, Inc.
Precision Edge
®
SY89429A
WITH 16MHZ INPUT
VCO Frequency
(MHz)
400
402
404
406
•
•
•
794
796
798
800
M Count
200
201
202
203
•
•
•
397
398
399
400
256
M8
0
0
0
0
•
•
•
1
1
1
1
128
M7
1
1
1
1
•
•
•
1
1
1
1
64
M6
1
1
1
1
•
•
•
0
0
0
0
32
M5
0
0
0
0
•
•
•
0
0
0
0
16
M4
0
0
0
0
•
•
•
0
0
0
1
8
M3
1
1
1
1
•
•
•
1
1
1
0
4
M2
0
0
0
0
•
•
•
1
1
1
0
2
M1
0
0
1
1
•
•
•
0
1
1
0
1
M0
0
1
0
1
•
•
•
1
0
1
0
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
I
I
OUT
T
store
T
A
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods
may affect device reliability.
Parameter
Power Supply Voltage
Input Voltage
Output Source
Storage Temperature
Operating Temperature
Continuous
Surge
Value
–0.5 to +7.0
–0.5 to +7.0
50
100
–65 to +150
–0 to +75
Unit
V
V
mA
°C
°C
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference
frequency of 2MHz.
The VCO within the PLL operates over a range of 400–800MHz.
Its output is scaled by a divider that is configured by either the
serial or parallel interfaces. The output of this loop divider is also
applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low) the PLL will not achieve loop lock. External
loop filter components are utilized to allow for optimal phase
jitter performance.
The output of the VCO is also passed through an output divider
before being sent to the PECL output driver. The output divider
is configured through either the serial or the parallel interfaces
and can provide one of four divider ratios (2, 4, 8 or 16). This
divider extends the performance of the part while providing a
50% duty cycle.
The output driver is driven differentially from the output divider
and is capable of driving a pair of transmission lines terminated
4
in 50½. The positive reference for the output driver is provided by
a dedicated power pin (V
CC_OUT
) to reduce noise and provide
application flexibility.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally upon system
reset, the P_
LOAD
input is held LOW until sometime after power
becomes valid. With S_
LOAD
held LOW, on the LOW-to-HIGH
transition of P_
LOAD
, the parallel inputs are captured. The parallel
interface has priority over the serial interface. Internal pull-up
resistors are provided on the M[8:0] and N[1:0] inputs to reduce
component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_
CLOCK
input. The serial input S_
DATA
must meet set-up and
hold timing as specified in the AC parameters section of this
data sheet. With P_
LOAD
held HIGH, the configuration latches
will capture the value in the shift register on the HIGH-to-LOW
edge of the S_
LOAD
input. See the programming section for more
information.
The TEST output reflects various internal node values and is
controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
Micrel, Inc.
Precision Edge
®
SY89429A
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
configuring the internal dividers to produce the desired
frequency at the outputs. The output frequency can be
represented by this formula:
The TEST output provides visibility for one of several
internal nodes (as determined by the T[1:0] bits in the serial
configuration stream). It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the TTL output may not be able to
toggle fast enough for some of the higher output frequencies.
The T2, T1, T0 configuration latches are preset to 000 when
P_LOAD is low, so that the FOUT outputs are as jitter-free as
possible. The serial configuration port can be used to select
one of the alternate functions for this pin.
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
bits of the data stream on the S_
DATA
input. For each register
the most significant bit is loaded first (T2, N1 and M8).
When T[2:0] is set to 100 the SY89429A is placed in PLL
bypass mode. In this mode the S_
CLOCK
input is fed directly
into the M and N dividers. The N divider drives the FOUT
differential pair and the M counter drives the TEST output
pin. In this mode the S_
CLOCK
input could be used for low
speed board level functional test or debug. Bypassing the
PLL and driving FOUT directly gives the user more control
on the test clocks sent through the clock tree (See detailed
Block Diagram). Because the S_
CLOCK
is a TTL level the input
frequency is limited to 250MHz or less. This means the fastest
the FOUT pin can be toggled via the S_
CLOCK
is 125MHz as
the minimum divide ratio of the N counter is 2. Note that the
M counter output on the TEST output will not be a 50% duty
cycle due to the way the divider is implemented.
Where F
XTAL
is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 M 400 for a 16MHz input reference.
M[8:0] and N[1:0] are normally specified once at power-on,
through the parallel interface, and then possibly again through
the serial interface. This approach allows the designer to
bring up the application at one frequency and then change or
fine-tune the clock, as the ability to control the serial interface
becomes available. To minimize transients in the frequency
domain, the output should be varied in the smallest step size
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