GTLP18T612MEA datasheet, PDF - EEWORLD Datasheet

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GTLP18T612MEA: DescriptionIC UNIV BUS TXRX 18BIT 56SSOP; Categorysemiconductor logic; File Size103KB，10 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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GTLP18T612MEA Overview

IC UNIV BUS TXRX 18BIT 56SSOP

GTLP18T612MEA Parametric

Parameter Name	Attribute value
logical type	universal bus transceiver
Number of circuits	18 bits
Current - output high, low	24mA，24mA
Voltage - Power	3.15 V ~ 3.45 V
Operating temperature	-40°C ~ 85°C
Installation type	surface mount
Package/casing	56-BSSOP (0.295", 7.50mm wide)
Supplier device packaging	56-SSOP

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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

May 1999

Revised July 2002

GTLP18T612

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP18T612 is an 18-bit universal bus transceiver

which provides LVTTL to GTLP signal level translation. It

allows for transparent, latched and clocked modes of data

transfer. The device provides a high speed interface for

cards operating at LVTTL logic levels and a backplane

operating at GTLP logic levels. High speed backplane

operation is a direct result of GTLP’s reduced output swing

(

1V), reduced input threshold levels and output edge rate

control. The edge rate control minimizes bus settling time.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different output

levels and receiver thresholds. GTLP output LOW level is

less than 0.5V, the output HIGH is 1.5V and the receiver

threshold is 1.0V.

Features

Bidirectional interface between GTLP and LVTTL logic

levels

Designed with edge rate control circuitry to reduce out-

put noise on the GTLP port

REF

pin provides external supply reference voltage for

receiver threshold adjustibility

Special PVT compensation circuitry to provide consis-

tent performance over variations of process, supply volt-

age and temperature

TTL compatible driver and control inputs

Designed using Fairchild advanced BiCMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

Open drain on GTLP to support wired-or connection

Flow through pinout optimizes PCB layout

D-type flip-flop, latch and transparent data paths

A Port source/sink

−

24mA/

24mA

B Port sink

50mA

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Order Number

GTLP18T612G

(Note 1)(Note 2)

GTLP18T612MEA

(Note 2)

GTLP18T612MTD

(Note 2)

Package Number

BGA54A

MS56A

MTD56

Package Description

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 1:

Ordering code “G” indicates Trays.

Note 2:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

DS500169

www.fairchildsemi.com

GTLP18T612MEA Related Products

	GTLP18T612MEA	GTLP18T612MEAX	GTLP18T612MTD	GTLP18T612MTDX
Description	IC UNIV BUS TXRX 18BIT 56SSOP	IC UNIV BUS TXRX 18BIT 56SSOP	IC UNIV BUS TXRX 18BIT 56TSSOP	IC UNIV BUS TXRX 18BIT 56TSSOP
logical type	universal bus transceiver	universal bus transceiver	universal bus transceiver	universal bus transceiver
Number of circuits	18 bits	18 bits	18 bits	18 bits
Current - output high, low	24mA，24mA	24mA，24mA	24mA，24mA	24mA，24mA
Voltage - Power	3.15 V ~ 3.45 V	3.15 V ~ 3.45 V	3.15 V ~ 3.45 V	3.15 V ~ 3.45 V
Operating temperature	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C
Installation type	surface mount	surface mount	surface mount	surface mount
Package/casing	56-BSSOP (0.295", 7.50mm wide)	56-BSSOP (0.295", 7.50mm wide)	56-TFSOP (0.240", 6.10mm wide)	56-TFSOP (0.240", 6.10mm wide)
Supplier device packaging	56-SSOP	56-SSOP	56-TSSOP	56-TSSOP

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