SY100S838ZI datasheet, PDF - EEWORLD Datasheet

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SY100S838ZI: Description(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHIP; Categorylogic logic; File Size523KB，5 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100S838ZI Overview

(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHIP

SY100S838ZI Parametric

Parameter Name	Attribute value
Parts packaging code	SOIC
package instruction	SOP, SOP20,.4
Contacts	20
Reach Compliance Code	compli
Is Samacsys	N
series	100S
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
length	12.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Maximum supply current (ICC)	75 mA
propagation delay (tpd)	1.22 ns
Same Edge Skew-Max（tskwd）	0.05 ns
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
minfmax	1000 MHz
Base Number Matches	1

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NOT RECOMMENDED FOR NEW DESIGNS

Micrel, Inc.

(

2/3) OR (

4/6)

CLOCK GENERATION CHIP

Precision Edge

Precision

SY100S838

Edge

SY100S838L

SY100S838

SY100S838L

FEATURES

■

3.3V and 5V power supply options

■

50ps output-to-output skew

■

Synchronous enable/disable

■

Master Reset for synchronization

■

Internal 75K

Ω

input pull-down resistors

■

Available in 20-pin SOIC package

Precision Edge

DESCRIPTION

The SY100S838/L is a low skew (÷1,

÷2/3)

or (÷2,

÷4/

6) clock generation chip designed explicitly for low skew

clock generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V

output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the V

output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The V

output is designed to act as the switching

reference for the input of the SY100S838/L under single-

ended input conditions. As a result, this pin can only

source/sink up to 0.5mA of current.

The Function Select (F

SEL

) input is used to determine

what clock generation chip function is. When FS

input

is LOW, SY100S838/L functions as a divide by 2 and by

4/6 clock generation chip. However, if FS

input is HIGH,

it functions as a divide by 1 and by 2/3 clock chip.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S838/Ls in a system.

TRUTH TABLE

CLK

Function

Divide

Hold Q

0–3

Reset Q

0–3

NOTES:

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

SEL

DIVSEL

OUTPUTS

Divide by 2

Divide by 1

OUTPUTS

Divide by 4

Divide by 6

Divide by 2

Divide by 3

PIN NAMES

CLK

SEL

DIVSEL

Function

Differential Clock Inputs

Function Select Input

Synchronous Enable

Master Reset

Reference Output

Differential

÷1

÷2

Outputs

Differential

÷2/3

÷4/6

Outputs

Frequency Select Input

Precision Edge is a registered trademark of Micrel, Inc.

M9999-113006

hbwhelp@micrel.com or (408) 955-1690

Rev.: G

Amendment: /0

Issue Date: November 2006

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