Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S321 is a monolithic 9-bit inverter. The device
contains nine inverting buffer gates with single input and
output.
PIN CONFIGURATIONS
D
4
V
CCA
V
EES
O
4
O
5
O
6
4
Top View
PLCC
J28-1
3
2
1
28
27
26
D
5
D
6
D
7
V
EE
V
EES
V
CCA
12
13
14
15
16
17
18
11 10 9 8 7 6 5
O
7
O
8
V
CCA
V
CC
V
CC
O
9
O
1
BLOCK DIAGRAM
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
O
1
O
2
D
8
D
9
19 20 21 22 23 24 25
V
CCA
O
3
O
2
D
1
D
2
D
3
V
EES
D
8
V
CCA
V
EE
D
9
D
7
D
1
O
3
O
4
O
5
O
6
O
7
O
8
O
9
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
D
6
D
5
D
4
V
CCA
Q
4
Q
5
Q
6
D
2
D
3
V
CCA
O
3
O
2
13
7 8 9 10 11 12
O
9
V
CC
O
1
PIN NAMES
Pin
D
1
– D
9
Q
1
– Q
9
V
EES
V
CCA
Function
Data Inputs
Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
V
CCA
Rev.: G
O
8
O
7
Amendment: /0
Issue Date: July, 1999
1
Micrel
SY100S321
DC ELECTRICAL CHARACTERISTICS
V
EE
= –4.2V to –5.5V unless otherwise specified, V
CC
= V
CCA
= GND
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
Min.
—
–55
Typ.
—
–41
Max.
200
–25
Unit
µA
mA
Condition
V
IN
= V
IH
(Max.)
Inputs Open
AC ELECTRICAL CHARACTERISTICS
CERPACK
V
EE
= –4.2V to –5.5V unless otherwise specified, V
CC
= V
CCA
= GND
T
A
= 0
°
C
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
S
, G–G
Parameter
Propagation Delay
(1)
Data to Output
Transition Time
(1)
20% to 80%, 80% to 20%
Skew, Gate-to-Gate
Min.
300
300
—
Max.
800
900
200
T
A
= +25
°
C
Min.
300
300
—
Max.
800
900
200
T
A
= +85
°
C
Min.
300
300
—
Max.
800
900
200
Unit
ps
ps
ps
Condition
NOTE:
1. Reference figures 1 and 2
PLCC
V
EE
= –4.2V to –5.5V unless otherwise specified, V
CC
= V
CCA
= GND
T
A
= 0
°
C
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
S
, G–G
Parameter
Propagation Delay
(1)
Data to Output
Transition Time
(1)
20% to 80%, 80% to 20%
Skew, Gate-to-Gate
Min.
300
300
—
Max.
700
900
200
T
A
= +25
°
C
Min.
300
300
—
Max.
700
900
200
T
A
= +85
°
C
Min.
300
300
—
Max.
700
900
200
Unit
ps
ps
ps
Condition
NOTE:
1. Reference figures 1 and 2
2
Micrel
SY100S321
TEST CIRCUITRY
(1)
L1
SCOPE
CHAN A
V
CC
R
T
0.1µF
PULSE
GENERATOR
L2
CIRCUIT
UNDER
TEST
SCOPE
CHAN B
R
T
V
EE
0.1µF
Figure 1. AC Test Circuit
NOTE:
1. V
CC
, V
CCA
= +2V, V
EE
= –2.5V.
L1 and L2 = equal length 50Ω impedance lines.
R
T
= 50Ω terminator internal to scope.
Decoupling 0.1µF from GND to V
CC
and V
EE
.
All unused outputs are loaded with 50Ω to GND.
C
L
= Fixture and stray capacitance
≤
3pF.
SWITCHING WAVEFORMS
0.7
±
0.1ns
0.7
±
0.1ns
–0.95V
INPUT
80%
50%
20%
–1.69V
t
PLH
t
PHL
80%
50%
20%
t
TLH
t
THL
OUTPUT
Figure 2. Propagation Delay and Transition Times
NOTE:
V
EE
= –4.2V to –5.5V unless otherwise specified, V
CC
= V
CCA
= GND
PRODUCT ORDERING CODE
Ordering
Code
SY100S321FC
SY100S321JC
SY100S321JCTR
Package
Type
F24-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
3
Micrel
SY100S321
24 LEAD CERPACK (F24-1)
Rev. 03
4
Micrel
SY100S321
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
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