SY100E241JC datasheet, PDF - EEWORLD Datasheet

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SY100E241JC: Description8-BIT SCANNABLE REGISTER; Categorylogic logic; File Size59KB，4 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100E241JC Overview

8-BIT SCANNABLE REGISTER

SY100E241JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microchip
package instruction	PLASTIC, LCC-28
Reach Compliance Code	_compli
Counting direction	RIGHT
series	100E
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.48 mm
Logic integrated circuit type	PARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Su	700000000 Hz
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Output characteristics	OPEN-EMITTER
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
power supply	-4.5 V
propagation delay (tpd)	0.975 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	11.48 mm
minfmax	700 MHz
Base Number Matches	1

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8-BIT SCANNABLE

SY10E241

SY100E241

FEATURES

1000ps max. CLK to output

Extended 100E V

range of –4.2V to –5.5V

SHIFT overrides HOLD, /LOAD control

Asynchronous Master Reset

Pin-compatible with E141

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E241

Available in 28-pin PLCC package

DESCRIPTION

The SY10/100E241 are 8-bit shiftable registers designed

for use in new, high-performance ECL systems. Unlike the

E141, the E241 features internal data feedback organized

such that the SHIFT control overrides the HOLD, /LOAD

control. Thus, the normal operations of HOLD and LOAD

can be toggled with a single control line without the need for

external gating. This configuration also enables switching

to scan mode with the single SHIFT control line.

The eight inputs D

–D

accept parallel input data, while

S-IN accepts serial input data when in shift mode. Data is

accepted a set-up time before the rising edge of CLK.

Shifting is also accomplished on the rising clock edge. A

HIGH on the Master Reset pin (MR) asychronously resets

all the registers to zero.

BLOCK DIAGRAM

S-IN

PIN CONFIGURATION

CCO

SEL

25 24 23 22 21 20 19

SEL

CLK

S-IN

10 11

CCO

– D

– Q

TOP VIEW

PLCC

J28-1

BITS 1-6

SEL

(HOLD/LOAD)

SEL

(SHIFT)

CLK

PIN NAMES

–D

S-IN

SEL

CLK

–Q

CCO

Function

Parallel Data Inputs

Serial Data Input

SHIFT Control

HOLD, /LOAD Control

Clock

Master Reset

Data Outputs

to Output

CCO

Rev.: C

Amendment: /1

Issue Date: February, 1998

SY100E241JC Related Products

	SY100E241JC	SY10E241JC	SY10E241JCTR	SY10E241	SY100E241JCTR
Description	8-BIT SCANNABLE REGISTER	8-BIT SCANNABLE REGISTER	8-BIT SCANNABLE REGISTER	8-BIT SCANNABLE REGISTER	8-BIT SCANNABLE REGISTER

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