SY100E193JZ datasheet, PDF - EEWORLD Datasheet

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SY100E193JZ: DescriptionERROR DETECTION/CORRECTION CIRCUIT; Categorylogic logic; File Size61KB，5 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100E193JZ Overview

ERROR DETECTION/CORRECTION CIRCUIT

SY100E193JZ Parametric

Parameter Name	Attribute value
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	unknow
Is Samacsys	N
series	100E
JESD-30 code	S-PQCC-J28
JESD-609 code	e3
length	11.48 mm
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	8
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	1.15 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	MATTE TIN
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.48 mm
Base Number Matches	1

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Micrel, Inc.

ERROR DETECTION/

CORRECTION CIRCUIT

SY10E193

SY100E193

SY10E193

SY100E193

FEATURES

Hamming code generation

Extended 100E V

range of –4.2V to –5.5V

8-bit wide

Expandable for more width

Provides parity register

Fully compatible with industry standard 10KH,

100K ECL levels

Internal75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E193

Available in 28-pin PLCC package

DESCRIPTION

The SY10/100E193 are error detection and correction

(EDAC) circuits designed for use in new, high- performance

ECL systems. The E193 generates hamming parity codes

on an 8-bit word as shown in the block diagram. The P

output gives the parity of the whole word. PGEN provides

word parity after Odd/Even parity control and gating with

the BPAR input. PGEN also feeds into a 1-bit shiftable

The combinatorial part of the device generates the same

code pattern as the Motorola MC10193.

Used in conjunction with 12-bit parity generators, such

as the E160, a SECDED (single error correction, double

error detection) error system can be designed for a multiple

of an 8-bit word.

PIN NAMES

–B

BPAR

EV/OD

HOLD

S-IN

SHIFT

CLK

–P

PGEN

PARERR/PARERR

CCO

Function

Check Bit Inputs

Check Bit Parity Input

Even/Odd Parity Select

Parity Enable

Syndrome Hold Input

Syndrome Bit Input

Syndrome Bit Shift

Clock Input

Parity Output

Parity Generate Output

Parity Error Output

to Output

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: March 2006

SY100E193JZ Related Products

	SY100E193JZ	SY10E193_06	SY10E193JZTR	SY10E193JZ	SY100E193JZTR
Description	ERROR DETECTION/CORRECTION CIRCUIT	ERROR DETECTION/CORRECTION CIRCUIT	ERROR DETECTION/CORRECTION CIRCUIT	ERROR DETECTION/CORRECTION CIRCUIT	ERROR DETECTION/CORRECTION CIRCUIT
Parts packaging code	QLCC	-	QLCC	QLCC	QLCC
package instruction	QCCJ,	-	QCCJ,	QCCJ,	QCCJ,
Contacts	28	-	28	28	28
Reach Compliance Code	unknow	-	unknow	unknow	unknow
series	100E	-	10E	10E	100E
JESD-30 code	S-PQCC-J28	-	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e3	-	e3	e3	e3
length	11.48 mm	-	11.48 mm	11.48 mm	11.48 mm
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT	-	ERROR DETECTION AND CORRECTION CIRCUIT	ERROR DETECTION AND CORRECTION CIRCUIT	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	8	-	8	8	8
Number of functions	1	-	1	1	1
Number of terminals	28	-	28	28	28
Maximum operating temperature	85 °C	-	85 °C	85 °C	85 °C
Output polarity	TRUE	-	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	-	QCCJ	QCCJ	QCCJ
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
propagation delay (tpd)	1.15 ns	-	1.15 ns	1.15 ns	1.15 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	-	4.57 mm	4.57 mm	4.57 mm
surface mount	YES	-	YES	YES	YES
technology	ECL	-	ECL	ECL	ECL
Temperature level	COMMERCIAL EXTENDED	-	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
Terminal surface	MATTE TIN	-	MATTE TIN	MATTE TIN	MATTE TIN
Terminal form	J BEND	-	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	-	QUAD	QUAD	QUAD
width	11.48 mm	-	11.48 mm	11.48 mm	11.48 mm

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