SY100E167JCTR datasheet, PDF - EEWORLD Datasheet

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SY100E167JCTR: Description6-BIT 2:1 MUX-REGISTER; Categorylogic logic; File Size182KB，3 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100E167JCTR Overview

6-BIT 2:1 MUX-REGISTER

SY100E167JCTR Parametric

Parameter Name	Attribute value
package instruction	QCCJ,
Reach Compliance Code	compli
Is Samacsys	N
Other features	SIX 2:1 MUX FOLLOWED BY REGISTER
series	100E
JESD-30 code	S-PQCC-J28
length	11.48 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	6
Number of functions	1
Number of terminals	28
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	0.8 ns
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Trigger type	POSITIVE EDGE
width	11.48 mm
minfmax	1000 MHz
Base Number Matches	1

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NOT RECOMMENDED FOR NEW DESIGNS

SEMICONDUCTOR

SYNERGY

6-BIT 2:1 MUX-REGISTER

SY10E167

SY100E167

SY10E167

SY100E167

FEATURES

1000MHz min. operating frequency

Extended 100E V

range of –4.2V to –5.5V

800ps max. clock to output

Single-ended outputs

Asynchronous Master Reset

Dual clocks

DESCRIPTION

The SY10/100E167 offer six 2:1 multiplexers followed

by D flip-flops with single-ended outputs, designed for use

in new, high-performance ECL systems. The Select (SEL)

control allows one of the two data inputs to the multiplexer

to pass through. The two external clock signals (CLK

CLK

) are gated through a logical OR operation before use

as control for the six flip-flops. The selected data are

transferred to the flip-flops on the rising edge of CLK

CLK

(or both).

The multiplexer operation is controlled by the Select

(SEL) signal which selects one of the two bits of input data

at each mux to be passed through.

When a logic HIGH is applied to the Master Reset (MR)

signal, it operates asychronously to take all outputs Q to a

logic LOW.

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

ESD protection of 2000V

Fully compatible with Motorola MC10E/100E167

Available in 28-pin PLCC package

BLOCK DIAGRAM

MUX

SEL

CLK

SEL

PIN CONFIGURATION

CCO

CLK

SEL

25 24 23 22 21 20 19

10 11

CCO

TOP VIEW

PLCC

J28-1

PIN NAMES

–D

SEL

CLK

, CLK

–Q

CCO

Function

Input Data a

Input Data b

Select Input

Clock Inputs

Master Reset

Data Outputs

to Output

Rev.: C

Amendment: /1

5-127

CCO

Issue Date: February, 1998

SY100E167JCTR Related Products

	SY100E167JCTR	SY10E167JCTR	SY10E167	SY10E167JC	SY100E167JC	SY100E167JC-TR	SY10E167JC-TR
Description	6-BIT 2:1 MUX-REGISTER	6-BIT 2:1 MUX-REGISTER	6-BIT 2:1 MUX-REGISTER	6-BIT 2:1 MUX-REGISTER	6-BIT 2:1 MUX-REGISTER	IC MUX/REGISTER 6-BIT 2:1 28PLCC	IC MUX/REGISTER 6-BIT 2:1 28PLCC

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