STK11C68 (SMD5962–92324)
8Kx8 SoftStore nvSRAM
FEATURES
• 25, 35, 45, and 55 ns Read Access & R/W Cycle
Times
• Unlimited Read/Write Endurance
• Pin compatible with Industry Standard SRAMs
• Software-initiated Non-Volatile
STORE
• Automatic
RECALL
to SRAM on Power Up
• Unlimited RECALL cycles
• 1 Million
STORE
Cycles
• 100-Year Non-volatile Data Retention
• Single 5V + 10% Operation
• Commercial, Industrial, and Military Tempera-
tures
• 28 pin 330 mil SOIC (RoHS-Compatible)
• 28-pin CDIP and LCC packages
DESCRIPTION
The Simtek STK11C68 is a 64Kb fast static RAM
with a nonvolatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use, and unlimited read & write endurance
of a normal SRAM.
Data transfers under software control to the non-vol-
atile storage cells (the
STORE
operation). On
power-up, data is automatically restored to the
SRAM (the
RECALL
operation). RECALL operations
are also available under software control.
The Simtek nvSRAM is the first monolithic non-
volatile memory to offer unlimited writes and reads.
It is the highest performance, most reliable non-
volatile memory available.
BLOCK DIAGRAM
BLOCK DIAGRAM
QUANTUM TRAP
128 x 512
ROW DECODER
A
5
A
6
A
7
A
8
A
9
A
11
A
12
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
0
– A
12
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0007 Rev 0.3
February, 2007
STK11C68 (SMD5962–92324)
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28-Pin LCC
28-Pin DIP
28-Pin SOIC
PIN NAMES
Pin Name
A
12
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
V
SS
Input
I/O
Input
Input
Input
Power Supply
Power Supply
I/O
Description
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, ±10%
Ground
Document Control #ML0007 Rev 0.3
February, 2007
2
STK11C68 (SMD5962–92324)
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1b
PARAMETER
MIN
Average V
CC
Current
MAX
90
75
65
N/A
3
10
27
23
20
N/A
750
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
–40
V
CC
+ .5
0.8
2.2
INDUSTRIAL/
MILITARY
MIN
MAX
90
75
65
55
3
10
28
24
21
20
1500
±1
±5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
UNITS
(V
CC
= 5.0V
±
10%)
NOTES
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
t
AVAV
= 55ns, E
≥
V
IH
E
≥
(V
CC
- 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
I
CC2c
I
CC3b
I
SB1d
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
I
SB2d
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
V
CC
+ .5 V
V
V
0.4
85
V
°C
V
SS
– .5 0.8
2.4
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
2
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
ΔV
= 0 to 3V
ΔV
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Output Capacitance
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
Document Control #ML0007 Rev 0.3
February, 2007
3
STK11C68 (SMD5962–92324)
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLd, e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
13
0
45
25
25
10
5
5
13
0
15
0
55
MIN
MAX
25
35
35
15
5
5
15
0
25
MIN
MAX
35
45
45
20
5
5
25
MIN
MAX
45
55
55
25
MIN
MAX
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK11C68-25
STK11C68-35
(V
CC
= 5.0V + 10%)
STK11C68-45
STK11C68-55
UNITS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
t
AVAV
ADDRESS
5
t
AXQX
3
2
t
AVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlled
f
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
11
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
ACTIVE
Document Control #ML0007 Rev 0.3
February, 2007
4
STK11C68 (SMD5962–92324)
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
5
MAX
MIN
55
45
45
30
0
45
0
0
35
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK11C68-25
STK11C68-35
(V
CC
= 5.0V + 10%)
STK11C68-45
STK11C68-55
UNITS
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1: W Controlled
j
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
SRAM WRITE CYCLE #2: E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
Document Control #ML0007 Rev 0.3
February, 2007
5
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