HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for bus
matching capability.
Dual chip enables allow for depth expansion without
external logic
◆
IDT7027S/L
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
CE
0L
CE
1L
OE
L
LB
L
R/
W
R
UB
R
CE
0R
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
A
14L
A
0L
32Kx16
MEMORY
ARRAY
7027
I/O
Control
I/O
Control
I/O
8-15R
I/O
0-7R
BUSY
R
A
14R
A
0R
(1,2)
.
Address
Decoder
A
14L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
Address
Decoder
A
14R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3199 drw 01
SEM
L
INT
L
(2)
M/S
(2)
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JULY 2004
DSC 3199/8
1
©2004 Integrated Device Technology, Inc.
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE
0
and
CE
1
) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. The IDT7027 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic
Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Pin Configurations
(1,2,3)
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
SEM
L
Vcc
R/W
L
OE
L
GND
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
NC
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
IDT7027PF
PN100-1(4)
100-Pin TQFP
Top View(5)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
07/23/04
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
NC
NC
LB
R
UB
R
CE
0R
CE
1R
SEM
R
GND
R/W
R
OE
R
GND
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
3199 drw 02
.
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
Vcc
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O1
L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
Vcc
I/O
7R
I/O
8R
I/O
9R
NC
2
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
07/23/04
81
80
77
74
72
69
68
65
63
60
57
54
12
A
10R
84
A
11R
83
A
14R
78
NC
76
UB
R
73
SEM
R
GND
70
67
GND
64
NC
61
I/O
13R
I/O
10R
59
56
NC
53
11
A
7R
87
A
8R
86
A
13R
82
NC
79
LB
R
75
CE
1R
R/W
R
71
66
GND I/O
14R
I/O
12R
I/O
9R
62
58
55
51
NC
50
10
09
08
A
4R
90
A
5R
88
A
9R
85
A
12R
NC
CE
0R
OE
R
I/O
15R
I/O
11R
NC
52
I/O
8R
49
I/O
7R
47
A
1R
92
A
3R
91
A
6R
89
NC
48
Vcc
46
I/O
5R
45
INT
R
95
A
0R
94
A
2R
93
I/O
6R
I/O
4R
44
43
I/O
3R
42
07
06
GND
96
M/S
BUSY
R
97
98
IDT7027G
G108-1
(4)
108-Pin PGA
Top View
(5)
I/O
2R
I/O
1R
39
40
I/O
0R
41
BUSY
L
INT
L
99
100
NC
102
I/O
1L
35
I/O
0L
37
GND
38
05
04
A
0L
101
A
1L
103
A
3L
106
I/O
4L
31
I/O
2L
34
GND
36
A
2L
104
A
4L
105
1
A
7L
4
8
12
17
21
25
Vcc
28
I/O
5L
32
I/O
3L
33
03
A
5L
107
2
A
6L
5
A
10L
7
A
13L
NC
10
CE
1L
13
GND
16
I/O
14L
I/O
10L
19
22
NC
24
I/O
7
L
29
I/O
6L
30
02
A
8L
108
3
A
11L
A
14L
6
9
NC
LB
L
D
UB
L
11
SEM
L
14
OE
L
15
GND I/O
13L
I/O
11L
18
20
23
26
NC
I/O
8L
27
01
A
9L
A
A
12L
B
NC
C
CE
0L
E
Vcc
F
R/W
L
G
NC
H
I/O
15L
I/O
12L
I/O
9L
J
K
L
NC
.
M
39
1 9drw 03
INDEX
Pin Names
Left Port
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3199 tbl 01
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
3
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable
CE
CE
0
V
IL
L
< 0.2V
V
IH
X
H
>V
CC
- 0.2V
X
CE
1
V
IH
>V
CC
- 0.2V
X
V
IL
X
<0.2V
Mode
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3199 tbl 02
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
2. Port "A" and "B" references are located where
CE
is used.
3. "H" = V
IH
and "L" = V
IL
.
Truth Table II – Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
Outputs
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3199 tbl 03
NOTES:
1. A
0L
— A
14L
≠
A
0R
— A
14R.
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
Inputs
(1)
CE
(2)
H
X
H
X
L
L
R/W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
Outputs
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
3199 tbl 04
______
______
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from all the I/Os (I/O
0
__
I/O
15
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
4
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1,3)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1)
Grade
Military
Ambient
Temperature
-55
O
C to+125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
3199 tbl 06
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
Commercial
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
3199 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Capacitance
(1)
Symbol
C
IN
C
OUT
(2)
(T
A
= +25°C, f = 1.0mhz) TQFP ONLY
Parameter
Input Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
9
10
Unit
pF
pF
3199 tbl 08
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3199 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. C
OUT
also references C
I/O
.
____
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7027S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
7027L
Max.
10
10
0.4
___
Min.
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3199 tbl 09
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc
<
2.0V, input leakages are undefined.
5
6.42
京公网安备 11010802033920号
EEWORLD
