AT49F002AN-55TU datasheet, PDF

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AT49F002AN-55TU: DescriptionIC FLASH 2M PARALLEL 32TSOP; Categorystorage; File Size1MB，20 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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AT49F002AN-55TU Overview

IC FLASH 2M PARALLEL 32TSOP

AT49F002AN-55TU Parametric

Parameter Name	Attribute value
memory type	non-volatile
memory format	flash memory
technology	FLASH
storage	2Mb （256K x 8）
Write cycle time - words, pages	50µs
interview time	55ns
memory interface	in parallel
Voltage - Power	4.5 V ~ 5.5 V
Operating temperature	-40°C ~ 85°C（TC）
Installation type	surface mount
Package/casing	32-TFSOP (0.724", 18.40mm wide)
Supplier device packaging	32-TSOP

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Features

•

Single-voltage Operation

– 5V Read

– 5V Reprogramming

Fast Read Access Time – 55 ns

Internal Program Control and Timer

Sector Architecture

– One 16K Bytes Boot Block with Programming Lockout

– Two 8K Bytes Parameter Blocks

– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)

Fast Erase Cycle Time – 4 Seconds

Byte-by-Byte Programming – 20 µs/Byte Typical

Hardware Data Protection

DATA Polling for End of Program Detection

Low Power Dissipation

– 30 mA Active Current

– 100 µA CMOS Standby Current

Typical 10,000 Write Cycles

Green (Pb/Halide-free) Packaging Option

•

2-megabit

(256K x 8)

5-volt Only

Flash Memory

AT49F002A

AT49F002AN

AT49F002AT

AT49F002ANT

Not Recommended

for New Design

Contact

Atmel to discuss

the latest design in trends

and options

•

1. Description

The AT49F002A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its

2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

55 ns with power dissipation of just 165 mW over the industrial temperature range.

When the device is deselected, the CMOS standby current is less than 100 µA. For

the AT49F002AN(T) pin 1 for the PLCC package and pin 9 for the TSOP package are

no connect pins.

To allow for simple in-system reprogrammability, the AT49F002A(N)(T) does not

require high input voltages for programming. Five-volt-only commands determine the

read and programming operation of the device. Reading data out of the device is sim-

ilar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus

contention. Reprogramming the AT49F002A(N)(T) is performed by erasing a block of

data and then programming on a byte-by-byte basis. The byte programming time is a

fast 20 µs. The end of a program cycle can be optionally detected by the DATA polling

feature. Once the end of a byte program cycle has been detected, a new access for a

read or program can begin. The typical number of program and erase cycles is in

excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device inter-

nally controls the erase operations. There are two 8K byte parameter block sections,

four main memory blocks, and one boot block.

The device has the capability to protect the data in the boot block; this feature is

enabled by a command sequence. The 16K-byte boot block section includes a repro-

gramming lock out feature to provide data integrity. The boot sector is designed to

contain user secure code, and when the feature is enabled, the boot sector is pro-

tected from being reprogrammed.

3354G–FLASH–3/05

4.3

Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic

high level, the device is in its standard operating mode. A low level on the RESET input halts the

present device operation and puts the outputs of the device in a high impedance state. If the

RESET pin makes a high to low transition during a program or erase operation, the operation

may not be successfully completed and the operation will have to be repeated after a high level

is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device

returns to the read or standby mode, depending upon the state of the control inputs. By applying

a 12V ± 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if

the boot block lockout feature has been enabled (see Boot Block Programming Lockout Over-

ride section). The RESET feature is not available for the AT49F002AN(T).

4.4

Erasure

Before a byte can be reprogrammed, the main memory block or parameter block which contains

the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device

can be erased at one time by using a 6-byte software code. The software chip erase code con-

sists of 6-byte load commands to specific address locations with a specific data pattern (please

refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are required. The maximum time needed to erase the whole chip

is t

. If the boot block lockout feature has been enabled, the data in the boot sector will not be

erased.

4.4.1

Chip Erase

If the boot block lockout has been enabled, the Chip Erase function will erase Parameter

Block 1, Parameter Block 2, Main Memory Block 1-4 but not the boot block. If the Boot Block

Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full

chip erase the device will return back to read mode. Any command during chip erase will be

ignored.

4.4.2

Sector Erase

As an alternative to a full chip erase, the device is organized into sectors that can be individually

erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8K-

byte parameter block sections and the four main memory blocks can be independently erased

and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector

address is latched on the rising WE edge of the sixth cycle and the 30H data input command is

also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the

sixth cycle. The erase operation is internally controlled; it will automatically time to completion.

AT49F002A(N)(T)

3354G–FLASH–3/05

AT49F002A(N)(T)

4.5

Byte Programming

Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte

basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is accomplished via the internal device command register

and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will

automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs

last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming

is completed after the specified t

cycle time. The DATA polling feature may also be used to

indicate the end of a program cycle.

4.6

Boot Block Programming Lockout

The device has one designated block that has a programming lockout feature. This feature pre-

vents programming of data in the designated block once the feature has been enabled. The size

of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that

is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This feature does not have to be activated;

the boot block’s usage as a write protected region is optional to the user. The address range of

the boot block is 00000 to 03FFF for the AT49F002A(N) while the address range of the boot

block is 3C000 to 3FFFF for the AT49F002A(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed

with input voltage levels of 5.5V or less. Data in the main memory block can still be changed

through the regular programming method. To activate the lockout feature, a series of six pro-

gram commands to specific addresses with specific data must be performed. Please refer to the

Command Definitions table.

4.6.1

Boot Block Lockout Detection

A software method is available to determine if programming of the boot block section is locked

out. When the device is in the software product identification mode (see Software Product Iden-

tification Entry and Exit sections) a read from address location 00002H will show if programming

the boot block is locked out for the AT49F002A(N), and a read from address location 3C002H

will show if programming the boot block is locked out for AT49F002A(N)T. If the data on I/O0 is

low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature

has been activated and the block cannot be programmed. The software product identification

exit code should be used to return to standard operation.

Boot Block Programming Lockout Override

The user can override the boot block programming lockout by taking the RESET pin to 12 volts.

By doing this, protected boot block data can be altered through a chip erase, sector erase or

word programming. When the RESET pin is brought back to TTL levels the boot block program-

ming lockout feature is again active. This feature is not available on the AT49F002AN(T).

4.6.2

3354G–FLASH–3/05

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