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MT28F004B3VG-8 BET TR

Description
IC FLASH 4M PARALLEL 40TSOP I
Categorystorage   
File Size440KB,30 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT28F004B3VG-8 BET TR Overview

IC FLASH 4M PARALLEL 40TSOP I

MT28F004B3VG-8 BET TR Parametric

Parameter NameAttribute value
memory typenon-volatile
memory formatflash memory
technologyFLASH - NOR
storage4Mb (512K x 8)
Write cycle time - words, pages80ns
interview time80ns
memory interfacein parallel
Voltage - Power3 V ~ 3.6 V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing40-TFSOP (0.724", 18.40mm wide)
Supplier device packaging40-TSOP I
4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
Features
• Seven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Four main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V V
CC
3.3V ±0.3V
V
PP
application programming
5V ±10%
V
PP
application/production programming
1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F400B3, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
(MT28F004B3, 512K x 8)
TSOP and SOP packaging options
MT28F004B3
MT28F400B3
3V ONLY, DUAL SUPPLY (SMART 3)
40-Pin TSOP Type I
48-Pin TSOP Type I
44-Pin SOP
GENERAL DESCRIPTION
The MT28F004B3 (x8) and MT28F400B3 (x16/x8)
are nonvolatile, electrically block-erasable (flash),
programmable memory devices containing 4,194,304
bits organized as 262,144 words (16 bits) or 524,288
bytes (8 bits). Writing or erasing the device is done with
either a 3.3V or 5V V
PP
voltage, while all operations are
performed with a 3.3V V
CC
. Due to process technology
advances, 5V V
PP
is optimal for application and pro-
duction programming. These devices are fabricated
with Micron’s advanced 0.18µm CMOS floating-gate
process.
The MT28F004B3 and MT28F400B3 are organized
into seven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
or overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv-
ing WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to
store code implemented in low-level system recovery.
The remaining blocks vary in density and are written
and erased with no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
Part Number Example:
Options
Timing
80ns access
Configurations
1 Meg x 8
512K x 16/1 Meg x 8
Boot Block Starting Word Address
Top (3FFFFh)
Bottom (00000h)
Operating Temperature Range
Extended (-40ºC to +85ºC)
Packages
MT28F004B3
Plastic 40-pin (standard) TSOP Type I
Plastic 40-pin (lead free) TSOP Type
I
MT28F400B3
Plastic 48-pin (standard) TSOP Type I
Plastic 48-pin (lead free) TSOP Type I
Plastic 44-pin (standard) SOP
Plastic 44-pin (lead free) SOP
Marking
-8
MT28F004B3
MT28F400B3
T
B
ET
VG
VP
WG
WP
SG
2
SP
2
NOTE:
1. This generation of devices does not support 12V
V
PP
production programming; however, 5V
V
PP
application production programming can be
used with no loss of performance.
2. Contact Factory for availability
MT28F400B3SG-8 T
09005aef8114a789
F45.fm - Rev. E 6/04 EN
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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